Junction Field Effect Transistor Device Research Articles

High-performance junction field-effect transistor based on black phosphorus/β-Ga2O3 heterostructure

Black phosphorous (BP), an excellent two-dimensional (2D) monoelemental layered p-type semiconductor material with high carrier mobility and thickness-dependent tunable direct bandgap structure, has been widely applied in various devices. As the essential building blocks for modern electronic and optoelectronic devices, high quality PN junctions based on semiconductors have attracted widespread attention. Herein, we report a junction field-effect transistor (JFET) by integrating narrow-gap p-type BP and ultra-wide gap n-type β-Ga2O3 nanoflakes for the first time. BP and β-Ga2O3 form a vertical van der Waals (vdW) heterostructure by mechanically exfoliated method. The BP/β-Ga2O3 vdW heterostructure exhibits remarkable PN diode rectifying characteristics with a high rectifying ratio about 107 and a low reverse current around pA. More interestingly, by using the BP as the gate and β-Ga2O3 as the channel, the BP/β-Ga2O3 JFET devices demonstrate excellent n-channel JFET characteristics with the on/off ratio as high as 107, gate leakage current around as low as pA, maximum transconductance (gm) up to 25.3 µS and saturation drain current (IDSS) of 16.5 µA/µm. Moreover, it has a pinch-off voltage of –20 V and a minimum subthreshold swing of 260 mV/dec. These excellent n-channel JFET characteristics will expand the application of BP in future nanoelectronic devices.

A Deep Insight into the Electronic Properties of CIGS Modules with Monolithic Interconnects Based on 2D Simulations with TCAD

The aim of this work is to provide an insight into the impact of the P1 shunt on the performance of ZnO/CdS/Cu(In,Ga)Se2/Mo modules with monolithic interconnects. The P1 scribe is a pattern that separates the back contact of two adjacent cells and is filled with Cu(In,Ga)Se2 (CIGS). This scribe introduces a shunt that can affect significantly the behavior of the device, especially under weak light conditions. Based on 2D numerical simulations performed with TCAD, we postulate a mechanism that affects the current flow through the P1 shunt. This mechanism is similar to that of a junction field effect transistor device with a p-type channel, in which the current flow can be modulated by varying the thickness of the channel and the doping concentration. The results of these simulations suggest that expanding the space charge region (SCR) into P1 reduces the shunt conductance in this path significantly, thus decreasing the current flow through it. The presented simulations demonstrate that two fabrication parameters have a direct influence on the extension of the SCR, which are the thickness of the absorber layer and its acceptor concentration.

CMOS-Integrated Low-Noise Junction Field-Effect Transistors for Bioelectronic Applications.

In this work, we present a CMOS-integrated low-noise junction field-effect transistor (JFET) developed in a standard 0.18 pm CMOS process. These JFETs reduce input-referred flicker noise power by more than a factor of 10 when compared to equally sized n-channel MOS devices by eliminating oxide interfaces in contact with the channel. We show that this improvement in device performance translates into a factor-of-10 reduction in the input-referred noise of integrated CMOS operational amplifiers when JFET devices are used at the input, significant for many applications in bioelectronics.

Carbon doped asymmetric cubic AlN/GaN multi quantum well structures for high electrical isolation to 3C‐SiC substrates

AbstractIn this work we present a novel method of the electrical separation of the substrate and the hetero junction field effect transistor device. For the epitaxial growth of our structures free standing 3C‐SiC (001) substrates with a free carrier concentration of n=2.7×1018 cm‐3 and a resistivity of ρ=34 mΩcm were used. On a 50 nm c‐GaN buffer layer an asymmetric multi quantum well structure consisting of 5 periodes of two cubic GaN:C asymmetric QWs (1 nm and 2 nm) embed‐ded between 3 nm thick c‐AlN:C barriers. A 50 nm c‐GaN cap layer completes the sample structure. A detailed conduction band profile and the quantized electron states within the asymmetric quantum well were calculated using a 1D Poisson‐Schrödinger‐solver. The structural properties were analyzed by atomic force microscopy and high resolution x‐ray diffraction. Current‐voltage measurements of these structures showed an increase of the serial resistivity by six orders of magnitude (from 5 mΩ to 8 kΩ) compared to an unstructured c‐GaN reference sample. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Switching Performance of Epitaxially Grown Normally-Off 4H-SiC JFET

Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6 – 10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5 – 1.8kV was realized at VGS = −5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design.

A JFET-CMOS Technology for Low-Noise Sensor Interface Circuits

In this paper, fabrication technology and device characteristics of junction field effect transistor (JFET) which can be integrated in CMOS sensor interface circuits are presented. The JFET is applicable to CMOS (operational) amplifiers to realize a very low-noise front-end amplifier in sensor interface circuits. It is formed with isolated p-well area in CMOS device. Extra processes to a standard CMOS technology are one photolithography process and two ion-implantation processes. N-type channel in JFET is formed by deep ion-implantation of phosphorous with energy of 150 keV to connect n+ source and drain regions. After that, p-type top gate region is formed by shallow ion-implantation of borron with energy of 30 keV. Fabricated JFET devices showed enough transconductance and low drain conductance, which are suitable to use them in analog amplifiers. Noise power-spectrum of the fabricated JFET was evaluated, and compared with n-MOSFET and p-MOSFET. As a result, noise-spectrum of JFET below 1 kHz was much lower than that of CMOS devices. Since many physical sensors have their signal bandwidth in low frequency band, this JFET device can be utilized in CMOS-based front-end amplifiers as the key device of low-noise sensor interface circuits.

The effect of high magnetic fields on junction field effect transistor device performance

We report measurements of the characteristics of a junction field effect transistor (JFET) in applied magnetic fields up to 30 T. For orientations parallel to the applied field, the device maintained a high transconductance (gfs) close to 80% of the zero field value. For field orientations perpendicular to the plane of current transport, gfs decreased by a factor of 6 at 30 T. This field dependence can be understood quantitatively in terms of the magnetoresistance associated with the cyclotron motion of current carriers within the conductive channels of the JFET. The results show that for suitable orientations the JFET may be used “in situ” for applications in very high fields.

A novel basis set for quantum calculations in MESFET and JFET devices

Sub-band occupation in MESFET (metal-semiconductor field-effect transistors) and JFET (junction field-effect transistor devices) has been modelled by use of a simple (sinusoidal) basis set. Such a simple basis set has easily evaluated matrix elements, allowing calculations to be easily performed. The authors have calculated sub-band energies and Fermi energy against electron concentration in these devices and find good agreement with previously calculated results. They have compared gate voltage/electron concentration curves calculated in their quantum model with the abrupt depletion approximation. The quantum curves show no structure and good agreement with the abrupt depletion model. This shows the abrupt depletion model to be an excellent approximation in these devices for electrostatic problems, even in the quantum limit (one occupied sub-band).

The effects of heavy doping on I– V characteristics of GaAs JFET and MESFET devices

The effects of heavy doping on the I– V characteristics and the transconductance of a heavily doped GaAs junction field-effect transistor (JFET) and a metal-semiconductor field-effect transistor (MESFET) are analyzed. Calculations were carried out by taking into account the heavy doping effects such as carrier degeneracy and bandgap narrowing. The results show that carrier degeneracy has a strong influence on the built-in potential in the junction between gate and channel and on the I– V characteristics of the heavily doped enhancement-mode JFET (E-JFET) and MESFET (E-MESFET) devices. These findings are important for modeling and design of heavily doped GaAs JFETs and MESFETs as well as other types of GaAs devices for VLSI applications.