Abstract
The aim of this work is to provide an insight into the impact of the P1 shunt on the performance of ZnO/CdS/Cu(In,Ga)Se2/Mo modules with monolithic interconnects. The P1 scribe is a pattern that separates the back contact of two adjacent cells and is filled with Cu(In,Ga)Se2 (CIGS). This scribe introduces a shunt that can affect significantly the behavior of the device, especially under weak light conditions. Based on 2D numerical simulations performed with TCAD, we postulate a mechanism that affects the current flow through the P1 shunt. This mechanism is similar to that of a junction field effect transistor device with a p-type channel, in which the current flow can be modulated by varying the thickness of the channel and the doping concentration. The results of these simulations suggest that expanding the space charge region (SCR) into P1 reduces the shunt conductance in this path significantly, thus decreasing the current flow through it. The presented simulations demonstrate that two fabrication parameters have a direct influence on the extension of the SCR, which are the thickness of the absorber layer and its acceptor concentration.
Highlights
The prospects of copper indium gallium diselenide-based solar cells (CIGS) as an alternative to traditional silicon solutions are growing with each efficiency achievement
This bias could be related to the built-in voltage (V bi ) of the device [16], which is the height of the barrier due to the space charge region (SCR)
The results of our work suggest a mechanism similar to the junction field effect transistor device (JFET) simplified model presented in reference [9]
Summary
The prospects of copper indium gallium diselenide-based solar cells (CIGS) as an alternative to traditional silicon solutions are growing with each efficiency achievement. Three devices are distinguished regarding their respective efficiencies, which are lab-scale, mini-modules, and modules. Regarding lab-scale devices, ZSW reported an efficiency of 22.6% [1], Solar Frontier reported the world record with an efficiency of 22.9% [2]. In the case of mini-module devices, 18.7% efficiency was reported by Solibro [3]. TSMC reported an efficiency of 16.5% for a full-size module in reference [4]. According to reference [5], improving the efficiency of lab scale cells could show the potential for improvement of large area interconnected devices. Optimization of ZnO window layers, absorbers and CIGS/CdS interfaces are found to be a key for the improvement of laboratory size devices [5]
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