JPEG Encoder Research Articles

LETAM: A low energy truncation-based approximate multiplier

In this paper, we propose an energy efficient approximate multiplier design obtained by truncating the input operands. In the structure, the n-bit multiplication operation is transformed to a smaller bit length multiplication plus some add and shift operations. The simple calculation core makes the multiplier a scalable yet low power structure. Also, we suggest an output quality-tunable multiplier providing ability to change the output quality during the multiplication operation. The characteristics of the proposed multiplier are compared with those of the exact and some other approximate multipliers in a 45 nm technology. The comparison reveals an average improvement of 89.2% (74.9%) in terms of the energy (area) compared to that of the exact multiplier. The utility of the proposed multiplier in a JPEG encoder application is also investigated. The results reveal that the Peak Signal to Noise Ratio (PSNR) reduction is at most 0.15 dB compared to that of the exact one.

Design and Implementation of a Gray Scale JPEG CODEC on Spartan-3E

This paper presents the design and implementation of the hardware JPEG CODEC for gray scale images. The architecture is designed in a way based on modules that a share between JPEG encoder and decoder circuit. Each module was designed to implement a forward and backward function and they have separate control signals. The JPEG CODEC (Compressor, Decompressor) architecture achieves high throughput with a deep and optimized pipeline, with a target to FPGA device implementation. The designed architectures are detailed in this paper and they are described in VHDL, simulated and physically mapped to XC3S500 FPGAs. The JPEG CODEC pipeline has a minimum latency of 166 clock cycles, that given the full modular pipeline depth. The CODEC could process a 512X 512 pixels still image in 5.2ms, reaching a maximum processing rate of 190 frames per second.

Design and Implementation of Gray Scale JPEG CODEC on Spartan-3E

This paper presents the design and implementation of the hardware JPEG CODEC for gray scale images. The architecture is designed in a way based on modules, all modules are sharing between JPEG encoder and decoder circuit . Each module was designed to implement forward and backward function and they have separate control signals. The JPEG CODEC (Compressor, Decompressor) architecture achieves high throughput with a deep and optimized pipeline, with a target to FPGA device implementation. The designed architectures are detailed in this paper and they were described in VHDL, simulated and physically mapped to XC3S500 FPGAs. The JPEG CODEC pipeline has a minimum latency of 166 clock cycles, given the full modular pipeline depth. The CODEC can process a 512x 512 pixels still image in 5.2ms, reaching a maximum processing rate of 190 frames per second. DOI: http://dx.doi.org/10.25130/tjes.24.2017.27

Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA

Digital imaging is omnipresent today. In many areas, digitized images replace their analog ancestors such as photographs or X-rays. The world of multimedia makes extensive use of image transfer and storage. The volume of these files is very high and the need to develop compression algorithms to reduce the size of these files has been felt. The JPEG committee has developed a new standard in image compression that now also has the status of Standard International: JPEG 2000. The main advantage of this new standard is its adaptability. Whatever the target application, whatever resources or available bandwidth, JPEG 2000 will adapt optimally. However, this flexibility has a price: the JPEG2000 perplexity is far superior to that of JPEG. This increased complexity can cause problems in applications with real-time constraints. In such cases, the use of a hardware implementation is necessary. In this context, the objective of this paper is the realization of a JPEG2000 encoder architecture satisfying real-time constraints. The proposed architecture will be implemented using programmable chips (FPGA) to ensure its effectiveness in real time. Optimization of renormalization module and byte-out module are described in this paper. Besides, the reduction in computational steps effectively minimizes the time delay and hence the high operating frequency. The design was implemented targeting a Xilinx Virtex 6 and an Altera Stratix FPGAs. Experimental results show that the proposed hardware architecture achieves real-time compression on video sequences on 35 fps at HDTV resolution.

Reversible Color-to-Gray Mapping with Resistance to the JPEG Encoding

Reversible Color-to-Gray Mapping with Resistance to the JPEG Encoding

An Efficient Video Compression Technique Using Watershed Algorithm and JPEG-LS Encoding

In the previous video compression method, the videos were segmented by using the novel motion estimation algorithm with aid of watershed method. But, the compression ratio (CR) of compression with novel motion estimation algorithm was not giving an adequate result. Moreover this methods performance is needed to be improved in the encoding and decoding processes. Because most of the video compression methods have utilized encoding techniques like JPEG, Run Length, Huffman coding and LSK encoding. The improvement of the encoding techniques in the compression process will improve the compression result. Hence, to overcome these drawbacks, we intended to propose a new video compression method with renowned encoding technique. In this proposed video compression method, the input video frames motion vectors are estimated by applying watershed and ARS-ST (Adaptive Rood Search with Spatio-Temporal) algorithms. After that, the vector blocks which have high difference value are encoded by using the JPEG-LS encoder. JPEG-LS have excellent coding and computational efficiency, and it outperforms JPEG2000 and many other image compression methods. This algorithm is of relatively low complexity, low storage requirement and its compression capability is efficient enough. To get the compressed video, the encoded blocks are subsequently decoded by JPEG-LS. The implementation result shows the effectiveness of proposed method, in compressing more number of videos. The performance of our proposed video compression method is evaluated by comparing the result of proposed method with the existing video compression techniques. The comparison result shows that our proposed method acquires high-quality compression ratio and PSNR for the number of testing videos than the existing techniques.

FPGA implementation of JPEG encoder architectures for wireless networks

Due to its relative simplicity, the JPEG compression algorithm requires less hardware or software resources with respect to new compression algorithms, for example the JPEG2000 and the JPEG XR. This makes it suitable for low-power applications. Moreover, features embedded in the JPEG2000 and the JPEG XR, such as the scalability of the image stream, can be added to the main JPEG core, making an encoder useful for example in a video surveillance wireless network. Nevertheless, actual JPEG dedicated hardware realizations do not implement many features of the compression standard. In this work, we developed several JPEG encoder architectures with full real-time reconfigurability and support for the restart intervals and, for a simple scalability mechanism, the scan scheme. These features make the architectures suitable for the use in low-bandwidth, low-power wireless networks. The JPEG encoder architectures have been developed starting from a SystemC model and then implemented in a FPGA.

Energy estimation in SystemC with Powersim

This paper presents a methodology to estimate the dissipation of energy in hardware, at any level of abstraction, with Powersim. Powersim is a C++ class library aimed to the calculation of energy dissipation of hardware described in SystemC. To this end C++ operators are monitored and a different energy model is used for each data type. Energy models are functions of operator inputs, constant parameters and variables, like supply voltage. The main advantage of this approach is that energy estimation does not require any change in the source code describing the hardware. As application examples, the computational complexity of a JPEG encoder, implemented in a FPGA, and a FIR filter, implemented in a microcontroller, are presented.

SEMG signal compression based on two-dimensional techniques.

BackgroundRecently, two-dimensional techniques have been successfully employed for compressing surface electromyographic (SEMG) records as images, through the use of image and video encoders. Such schemes usually provide specific compressors, which are tuned for SEMG data, or employ preprocessing techniques, before the two-dimensional encoding procedure, in order to provide a suitable data organization, whose correlations can be better exploited by off-the-shelf encoders. Besides preprocessing input matrices, one may also depart from those approaches and employ an adaptive framework, which is able to directly tackle SEMG signals reassembled as images.MethodsThis paper proposes a new two-dimensional approach for SEMG signal compression, which is based on a recurrent pattern matching algorithm called multidimensional multiscale parser (MMP). The mentioned encoder was modified, in order to efficiently work with SEMG signals and exploit their inherent redundancies. Moreover, a new preprocessing technique, named as segmentation by similarity (SbS), which has the potential to enhance the exploitation of intra- and intersegment correlations, is introduced, the percentage difference sorting (PDS) algorithm is employed, with different image compressors, and results with the high efficiency video coding (HEVC), H.264/AVC, and JPEG2000 encoders are presented.ResultsExperiments were carried out with real isometric and dynamic records, acquired in laboratory. Dynamic signals compressed with H.264/AVC and HEVC, when combined with preprocessing techniques, resulted in good percent root-mean-square difference times compression factor figures, for low and high compression factors, respectively. Besides, regarding isometric signals, the modified two-dimensional MMP algorithm outperformed state-of-the-art schemes, for low compression factors, the combination between SbS and HEVC proved to be competitive, for high compression factors, and JPEG2000, combined with PDS, provided good performance allied to low computational complexity, all in terms of percent root-mean-square difference times compression factor.ConclusionThe proposed schemes are effective and, specifically, the modified MMP algorithm can be considered as an interesting alternative for isometric signals, regarding traditional SEMG encoders. Besides, the approach based on off-the-shelf image encoders has the potential of fast implementation and dissemination, given that many embedded systems may already have such encoders available, in the underlying hardware/software architecture.

Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications

Error-resilient applications such as image, audio and video processing adopt the concept of approximate computing to decorate delay, power and area metrics at the cost of accuracy. Approximate computing relaxes the exact equivalence between the design specifications and the design implementation to achieve Speed-Power-Accuracy-Area (SPAA) trade-off. In this paper, we propose a bit-width-aware constant-delay run-time Accuracy Programmable Adder (APA) in which the probability of input combinations exhibiting accurate results is programmable and adaptively controlled by the Number of Iterations (NoIs). Simulation results based on the PTM 32nm CMOS technology suggest that the proposed approach attains tremendous improvements in delay, power and area metrics with a trivial degradation in the output quality. The proposed APA shows 3.4 × improvement in performance and 41.5% reduction in area over the best known accuracy configurable adder. Even with 100% accuracy, a 32-bit APA improves delay, power and area by 33.92%, 23.04% and 17.44%, respectively, over Ripple Carry Adder (RCA). We also demonstrate an APA embedded error-resilient JPEG encoder architecture in order to inspect the efficacy of the proposed approach in real-time Digital Signal Processing (DSP) applications.

Simultaneous accelerator parallelization and point-to-point interconnect insertion for bus-based embedded SoCs

As performance requirements for bus-based embedded System-on-Chips(So Cs) increase, more and more on-chip application-specific hardware accelerators(e.g., filters, FFTs, JPEG encoders, GSMs, and AES encoders) are being integrated into their designs. These accelerators require system-level tradeoffs among performance, area, and scalability. Accelerator parallelization and Point-to-Point(P2P) interconnect insertion are two effective system-level adjustments. The former helps to boost the computing performance at the cost of area,while the latter provides higher bandwidth at the cost of routability. What’s more, they interact with each other. This paper proposes a design flow to optimize accelerator parallelization and P2 P interconnect insertion simultaneously.To explore the huge optimization space, we develop an effective algorithm, whose goal is to reduce total So C latency under the constraints of So C area and total P2 P wire length. Experimental results show that the performance difference between our proposed algorithm and the optimal results is only 2.33% on average, while the running time of the algorithm is less than 17 s.

Instrumentation-Driven Validation of Dataflow Applications

Dataflow modeling offers a myriad of tools for designing and optimizing signal processing systems. A designer is able to take advantage of dataflow properties to effectively tune the system in connection with functionality and different performance metrics. However, a disparity in the specification of dataflow properties and the final implementation can lead to incorrect behavior that is difficult to detect. This motivates the problem of ensuring consistency between dataflow properties that are declared or otherwise assumed as part of dataflow-based application models, and the dataflow behavior that is exhibited by implementations that are derived from the models. In this paper, we address this problem by introducing a novel dataflow validation framework (DVF) that is able to identify disparities between an application's formal dataflow representation and its implementation. DVF works by instrumenting the implementation of an application and monitoring the instrumentation data as the application executes. This monitoring process is streamlined so that DVF achieves validation without major overhead. We demonstrate the utility of our DVF through design and implementation case studies involving an automatic speech recognition application, a JPEG encoder, and an acoustic tracking application.

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors' best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.

Multilevel MPSoC Performance Evaluation: New ISSPT Model

To deploy the enormous hardware resources available in Multi Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, methods of Design Space Exploration (DSE) are needed to evaluate the different design alternatives. In this paper, we present a framework that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the Transaction Level Modeling (TLM) approach, we present a new definition of ISS level by introducing two complementary modeling sublevels ISST and ISSPT. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder. The performance of the proposed approach has been analyzed in our platform MPSoC based on multi-MicroBlaze. Simulation results show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin. DOI: http://dx.doi.org/10.11591/telkomnika.v15i1.8085

Energy‐efficient illumination‐invariant change detection in DCT coefficient domain for vehicular black box camera

An energy-efficient and highly accurate change detection method for a vehicular black box system by utilising information in a compressed domain is presented. Studies have shown that most automobiles spend a substantial percentage of time parked rather than driven. Thus, minimising energy consumption in a parked mode is crucial for vehicular black box systems design to prevent the battery being fully discharged. To meet a low energy requirement in parked mode, a hybrid video encoding engine with JPEG for parked and H.264 for driving mode is used. A change detection method is devised for parked mode using the JPEG encoder. The proposed change detection method detects events by utilising discrete cosine transform (DCT) coefficients that are readily available from the JPEG encoder at no extra computing cost. By using the ratio AC coefficients to a DC coefficient in each DCT block, illumination-resistant change detection has been successfully achieved. The illumination-invariant detection reduced the false positives while maintaining a very low false negative ratio. Experimental results demonstrate that the proposed method achieves 25.6–24.2% lower energy consumption and 25.4–1.2% better accuracy in illumination-varying circumstances compared with existing illumination-independent change detection algorithms.

AN EEP TRANSMISSION SYSTEM USING RCPT CODES AND JPEG2000

This work describes a method for providing robustness to errors from a binary symmetric channel for the JPEG2000 image compression. The source rate and channel rate are jointly optimized by a stream of fixed-size channel packets. Punctured turbo codes are used for the channel coding, providing stronger error protection than previously available codes. We use a subset of the puncturing patterns that are well chosen and that leads to the best source rate. The rate allocation scheme presented obtains all necessary information from the JPEG2000 encoder, and does not require image decompression.

Embedded network camera processor system on a chip for various low-power multimedia applications

In this paper we present an embedded network camera processor (NCP) system on a chip (SoC) for various low-power multimedia applications. The NCP SoC comprises a digital camera processor optimized for a CCD sensor, a motion JPEG encoder to compress the data, an Ethernet controller to transmit the data, ARM processor and many peripherals. Using the NCP SoC allows the raw image from a CCD sensor to be filtered, compressed and transmitted anywhere through various Ethernet protocols, with no additional hardware. The NCP SoC is designed with Verilog-HDL. Also, we followed a strict ASIC flow including functional behavior verification and a scan test. The NCP SoC is fabricated with 0.25 $${\upmu }{\text {m}}$$μm CMOS technology. The total chip size, including embedded memory, is $$7800\times 7800\,{\upmu }{\text {m}}^{2}$$7800×7800μm2 and the gate count is 1.2 million. The NCP SoC runs at up to 48 MHz, and supports various slower clock frequencies for low-power applications requiring additional power saving modes: 6 MHs, 12 and 24 MHz at 2.5 V.

Color Rendering of Images in the Internet and Print Reproductions of the Sistine Chapel’s Frescos

ABSTRACTMany digital reproductions of artefacts can be found on the Internet. In this study we investigate differences between original works of art and digital reproductions downloaded from several online databases. Four frescos in the Sistine Chapel were selected for detailed investigation. Representative colored patches were measured on these reproductions from the Internet and from two printed albums. These data were compared with the Vatican Museum’s measurements of the original frescos and measurements in the Sistine Chapel taken by the researchers of the Virtual Environments and Imaging Technologies Laboratory of the University of Pannonia. Results presented in this article demonstrate that there are significant differences between the original artefacts and their digital reproductions. The source of these differences is very complex. One is the difference between the displaying techniques of different web browsers, which produces relevant aberrations in color rendering. Differences can also arise from the JPEG encoding and decoding methods. Implicit use of color spaces in browsers, missing or incorrect EXIF data, and noncalibrated displays together can result in very different forms of representation.

Acceleration of Tests for the JPEG2000 Encoder Verification

The paper presents a new approach to improve efficiency of the verification process through acceleration of tests. The verification eco-system based on well-accepted industry standards, consisting of essential functionality and an emulation platform is described in the article. The JPEG2000 encoder has been developed with the use of this emulation platform in order to verify both, the new approach and the possibility of reducing verification process time. The new approach allows to save verification time, due to significant reduction of tests execution time. Additionally, a debug capability, which is provided by the emulation system, enables quick identification and elimination of implementation bugs. The presented solution can be supported by Universal Verification Methodology (UVM) like methodology to create the best suited environment. In order to use such methodology, the SystemC language has been enhanced by UVM-SystemC library. The library in combination with the approach presented in the paper and the use of the emulation platform can deliver the complete system to verify IP cores of average complexity. It gives an opportunity to avoid a commercial logic simulator within the verification process.

An Evaluation of Security and Privacy Threats for Cloud-based Applications

Abstract Cloud computing system provides virtual IT infrastructures with a set of resources that are shared with multi-tenant users. Data Privacy and the security are major challenges when users outsource their data to a cloud. Privacy can be violated by the cloud vendor, vendor's authorized users, other cloud users, unauthorized users, or external malicious entities. Encryption is one of the solutions to protect and maintain privacy of cloud-stored data. However, encryption methods are complex and expensive for mobile devices. In this workshop, we review major literatures and we introduce our previous study about a light-weight method for mobile clients to store data on one or multiple clouds by using pseudo-random permutation based on chaos systems. The method can be used in client mobile devices to store data in the cloud(s) without using cloud computing resources for encryption to maintain user's privacy. We consider JPEG image format as a case study to present and evaluate the proposed method. Our results show that the proposed method achieves superior compare to encryption methods, such as AES and encryption on JPEG encoders while protecting the mobile user data privacy.