Bandwidth Jitter Research Articles

A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.

Investigation of noise amplification questions in satellite jitter detected from CCDs’ parallax observation imagery: A case for 3 CCDs

Parallax observations from adjacent CCDs have been applied to detect satellite jitter, and the highest detectable jitter frequency reaches up to half CCDs image line frequency, among which, however, not all frequencies’ jitter could be detected accurately. Jitter error mainly comes from the noise in offset data. In this research, it is found that at some frequencies the noise is amplified significantly, leading to seriously deviated jitter components and even unreliable jitter results. This research focuses on the noise-amplifying questions in jitter detection and explores what CCD parameters determine them. Firstly, the error transfer coefficients (ETC) between jitter and offset is derived, and the frequencies are divided into three categories: blind frequencies, noise-amplifying frequencies and noise-suppressing frequencies. Secondly, for two adjacent CCDs, formulas are established to determine their blind frequencies and noise-amplifying bands, which indicate that it is the two CCDs’ image line time t r and the distance l between the two CCDs’ first lines that determine their blind frequencies and noise-amplifying bands. The reciprocal of the product of t r and l is defined as the fundamental frequency F of the CCD pair. As a result, the blind frequencies and noise-amplifying bands both reoccur with a period of fundamental frequency F , but unlike those isolated bind frequencies, the noise-amplifying bands span much wider, up to nearly 1/3 jitter bandwidth . Thirdly, for three adjacent CCDs forming two CCD pairs, aliasing between the two pairs’ noise-amplifying bands is first proven to be inevitable and reoccurs in cycles. Formulas are then established to extract the aliasing components and compute the aliasing period length. Experiments and simulations are conducted to test the constructed theories. Results show that the RMSE is 7.127 × 1 0 − 5 Hz for blind frequencies formulas, and the RRMSEs are 0.0051% for noise-amplifying bands’ period formulas, 0.0033% for aliasing period, and 1.2610% for noise-amplifying bandwidth, proving that the established formulas could generate reliable results for the blind frequencies, noise-amplifying bands and their aliasing components of three adjacent CCDs. Our studies are expected to help analyze more CCDs’ noise-amplifying problems and provide a prospect to reduce their impact on jitter detection by optimizing CCD parameter values. • Blind frequencies (BFs) and noise-amplifying bands (NABs) are discovered in jitter detection. • BFs and NABs cause loss of accuracy in satellite jitter detection. • NABs span much wider bands than BFs, up to nearly 1/3 jitter estimation bandwidth. • Theories are constructed to determine BFs and NABs. • The theories reveal what patterns BFs and NABs follow and what parameters determine them.

Generation of synchronized picosecond pulses by a 1.06-µm gain-switched laser diode for stimulated Raman scattering microscopy.

We propose that a gain-switched laser diode (GS-LD) can be used as a picosecond laser source for stimulated Raman scattering (SRS) microscopy. We employed a 1.06-µm GS-LD to generate ~13-ps pulses at a repetition rate of 38 MHz and amplified them to >100 mW with Yb-doped fiber amplifiers. The GS-LD was driven by 200-ps electrical pulses, which were triggered through a toggle flip-flop (T-FF) so that the GS-LD pulses were synchronized to Ti:sapphire laser (TSL) pulses at a repetition rate of 76 MHz. We found the timing jitter of GS-LD pulses to be approximately 2.7 ps in a jitter bandwidth of 7 MHz. We also show that the delay of electrical pulses can be less sensitive to the optical power of TSL pulses by controlling the threshold voltage of the T-FF. We demonstrate the SRS imaging of polymer beads and of HeLa cells with GS-LD pulses and TSL pulses, proving that GS-LD is readily applicable to SRS microscopy as a compact and stable pulse source.

Global Positional Proportional Fairness Based on Spectrum Aggregation in Cognitive Radio

In cognitive radio system, when spectrum aggregation technology is involved to support numerous data transmission, it is still a problem that band resources scheduling is unfairness among secondary users. A global positional proportional fairness scheduling algorithm is investigated based on spectrum aggregation to clarify the problem. This paper focuses on the relationship between spectrum aggregation and fairness scheduling of secondary users. Bandwidth fairness can be improved by considering the positional parameters if secondary users are at disadvantage locations which make the band resources restricted. Simulation results show that the proposed scheduling algorithm takes advantages of bandwidth fairness comparing with the traditional scheduling algorithms without positional parameters. Meanwhile it presents that the proposed fairness scheduling algorithm sacrifice bandwidth jitter index to make sure of fairness among secondary users.

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Reversible logic is becoming one of the best emerging design approaches for future computation of reversible logic having its more application in low power application. This logic is applied in the quantum computers, optical computing, communication and nanotechnology. In reversible logic approach generates the garbage input/output. In this paper design of proposed reversible logic multiplexer with garbage input/output, that the low power, area design technique are using that is the Gate -Diffusion -Input (GDI cell) in this dynamic component of power is reduced, In GDI cell PMOS is not connected to supply voltage VDD and NMOS is not connected to the GND.GDI circuits provide some measure issues of enhanced hazard tolerance and low voltage operation of reversible logic circuits. In this paper propose a novel application of GDI (Gate-Diffusion Input) circuits to Reversible logic multiplexer with its Garbage input and output. The new proposed design technique will consume less power than the other traditional gate. In recent years ago reversible logic circuit is less power dissipation. This GDI cell technique reduces the power of the circuit, delay, PowerDelay Product (PDP) and it also reduced frequency. The device scaling is limited by the power dissipation are more optimize in terms of delay, power supply, frequency , duty cycle, frequency jitter bandwidth of the signal and also demonstrated the noise of the circuit. The proposed reversible logic design. the GDI is effective in low power, low leakage current and lower Delay, The transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm technology, some of the trade-offs are made in the design to improve the efficiency.

An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors

We present an 8.0-Gb/s HyperTransport source-synchronous I/O integrated in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design capping at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels by incorporating several jitter- and power-reduction enhancements. First, a high-bandwidth digital clean-up PLL is introduced to attenuate high-frequency jitter in the received forwarded clock before the data is sampled. This PLL achieves a highly programmable jitter bandwidth of 20-296 MHz (measured with 0.2 UI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> input jitter) and 0.90-1.50 ps output rms jitter by implementing an extended bang-bang phase detector for additional phase-error magnitude information and flexible bang-bang control of a current-starved ring-based oscillator. Second, several power-hungry circuits, namely the transmitter input FIFO and output driver as well as the receiver deserializer, are redesigned for 8.0-Gb/s operation to maintain thermal compatibility with the existing 45-nm socket package. The fabricated 20-lane I/O consumes 1.70 W at 8.0 Gb/s with an energy efficiency of 11.8 pJ/bit. This reflects a 4.9% increase in HyperTransport power consumption and only 0.3% increase in total processor target power relative to 45-nm operation at 6.4 Gb/s.

Effect and Compensation of Colored Timing Jitter in Pulsed UWB Systems

Ultra-wideband (UWB) systems impose a stringent requirement on the jitter performance of the system clock. So far, only the effect of white Gaussian timing jitter has been considered in the literature via numerical simulation. However, practical clocks commonly exhibit colored jitter. In this paper, we first investigate the bit error rate (BER) performance of a single-user binary pulse position modulation UWB system subjected to white and colored Gaussian jitter. It is shown that colored jitter degrades BER performance much more than white jitter, and the extent of degradation increases as the jitter bandwidth decreases. Motivated by this result, we then propose a new jitter compensation scheme to improve the BER performance under colored jitters with small jitter bandwidth, in which each information-bearing data symbol is coupled with a pilot symbol. The proposed scheme attempts to track first the jitter for the current pilot symbol by making use of the pulse-template correlation function. This information is then used together with the known clock jitter bandwidth and jitter root-mean-square (RMS) value to detect the current data symbol according to the maximum likelihood criterion. Simulation results show that the algorithm is effective in improving the BER performance for colored jitters with small jitter bandwidth.

Long term laser frequency control for applications in atomicphysics

An improvement to the saturated absorption technique of long termstabilization of lasers is reported. This new method enables stabilization to the centreof saturated absorption features regardless of whether the peaks are symmetricor asymmetric. Another feature of the locking system is its ability to stabilizethe laser at precisely known small detunings from the centre of the absorptionline. The locking system has been applied to both dye laser and titaniumsapphire laser systems. The long term drift for each was measured to be smallerthan the laser jitter bandwidth of about 1 MHz for periods of hours, and no modehops were recorded over several weeks of operation.

Phase-Locked Loops with Signal Injection for Increased Pull-In Range and Reduced Output Phase Jitter

Second-order phase-locked loops with signal injection (PLLI's) have orders of magnitude larger pull-in ranges than conventional second-order PLL's with identical natural frequencies and damping factors. The PLLI utilizes a little-known characteristic of the Van der Pol oscillator, and for practically no additional hardware the pullin range is increased sufficiently to eliminate in many cases the need for crystal control of the voltage-controlled oscillator (VCO). In nonlinear systems (e.g., a retiming chain of a digital repeater) where the in-phase and in-quadrature noise components are correlated, the PLLI in addition features a significant reduction in output phase jitter. A 44.6MHz PLLI, designed for timing recovery in a fiber optic repeater, has 8.4-kHz conventional minimum jitter bandwidth. To reduce time jitter accumulation in a chain of repeaters, the damping factor was increased to 4 resulting in a Q of 1300. The pull-in range of this loop is 9.6 MHz compared to 18 kHz for the same loop without signal injection. The static phase error is \pm 0.6\deg for ± 0.3 MHz oscillator drift. By injecting with 18° phase lag, the PLLI can take advantage of the correla tion between amplitude and phase noise components and the total output phase jitter is reduced by 10.5 dB due to destructive interference.