Jitter Transfer Research Articles

Timing Jitter Transfer Function in the Temporal Talbot Effect

We report the predicted timing jitter transfer function for the temporal Talbot effect. The results, consistent with previous theoretical analyses, indicate a clear low-pass-like behavior, with significant jitter attenuation below a specific jitter cutoff frequency, and visible resonant peaks for frequencies satisfying secondary Talbot conditions. The observed transfer function makes the Talbot effect especially interesting for jitter mitigation in all-optical clock schemes.

A 9.95–11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS

A 9.95-11.3-Gb/s transceiver in 0.13-mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12'' of FR4 is equalized resulting in system JGEN under 4 mUI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> and 35 mUI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> . Power consumption is 800 mW

Improvement of jitter transfer characteristics of a 9.95328 Gb/s data recovery DLL using saw filter

This paper presents a design of a high-speed data recovery circuit for non return zero (NRZ) data transmission using delay-locked loop (DLL) with SAW filter. The jitter generation of the circuit is decreased by adjusting the loop gain in DLL whereas surface acoustic wave (SAW) filter with low centered frequency ( f c) improves the jitter transfer function of DLL. It is seen that the circuit using SAW filter of f c = 1.24416 GHz and Q = 1000 provides the cut off frequency of about 600 kHz which is ∼10 times lower than that of conventional DLL circuit.

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-&lt;tex&gt;$muhbox m$&lt;/tex&gt;CMOS

A clock and data recovery (CDR) architecture featuring a parallel phase detector is proposed for speeding up linear-type CDRs. A cause of speed limit in conventional CDRs is very short UP pulses in its phase detector circuit. The parallel phase detector expands UP pulsewidth by adding fixed-width using a half-rate clock. The parallel phase detector is used in the CDR with a couple of unbalanced charge-pump. The bandwidth of decision latches of the PD is extended by 1.7 times by using both shunt-peaking and capacitance coupling. The monolithic CDR implemented in 0.13-mum CMOS shows 1.7 times wider phase linear response region of 0.56UI than that of a conventional CDR. It operates at 12.5-Gb/s with PRBS 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 input data. Measurements show large jitter tolerance of over 0.5 UIpp for 4-8 MHz jitter frequency as well as jitter transfer characteristics independent on input-jitter amplitudes of 0.1, 0.3, and 0.5 UIpp

Standard-compliant jitter transfer function of all-optical clock recovery at 40 GHz based on a quantum-dot self-pulsating semiconductor laser

This letter reports on all-optical clock recovery over 40-Gb/s signal using a quantum-dot (QD)-based self-pulsating (SP) laser. In particular, the jitter transfer function from the input signal to the recovered clock is measured for the first time. We clearly demonstrate that, thanks to the narrow spectral linewidth of the free-running SP signal, the QD-based laser allows the suppression of high frequency jitter, and the cutoff frequency is exactly that required by the ITU-T recommendation G825.1 at 40 GHz

A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback

A continuous-rate clock and data recovery (CDR) circuit that operates from 12.5 Mb/s to 2.7 Gb/s is described. The circuit automatically detects a change in input data rate, acquires the new frequency, and reports the data rate to the user without the need for an external reference clock or any programming. At 2.5Gb/s, it achieves an acquisition time of 1 ms. In tracking mode, it uses a dual DLL/PLL to provide superior jitter performance compared to a standard second-order loop. At the OC48 data rate, it achieves a jitter transfer bandwidth of 500 kHz and a jitter tolerance bandwidth of 3 MHz. It is on a 0.35-/spl mu/m double-poly, triple-metal (DPTM) BiCMOS process, dissipates 235 mA from a 3.3-V supply, and occupies 9 mm/sup 2/. It is in a compact 5/spl times/5 mm/sup 2/ LFCSP package.

Optical clock recovery circuits using traveling-wave electroabsorption modulator-based ring oscillators for 3R regeneration

We describe an optical clock recovery circuit that employs a traveling-wave electroabsorption modulator-based ring oscillator. This approach provides synchronized optical clock and the original optical data signal from the same output at separate wavelengths, eliminating additional timing adjustments for the subsequent nonlinear decision gate for reamplifying, reshaping, and retiming (3R) regeneration. Furthermore, additional retiming and lateral reshaping of the original data signal can be realized along with optical clock recovery by synchronized modulation. We present a general model of jitter transfer and locking dynamics for the clock recovery circuit and compare with experimental results. Theoretical results indicate that by using hybrid integration to shorten the cavity length, nanosecond-order locking time can be achieved, which is critical for a variety of applications such as protection switching, optical burst and optical packet switching. Experimental demonstrations of 40-Gb/s optical clock recovery and its application for optical 3R regeneration are presented. The recovered 40-GHz optical clock has 500-fs timing jitter and 8-ps pulsewidth, and within 0.3 /spl mu/s locking time. 3R experiment is implemented by using the OCR combined with a subsequent regenerative wavelength converter, which provides vertical reshaping function. 3R regeneration is demonstrated with a reduced timing jitter.

Analysis and modeling of bang-bang clock and data recovery circuits

A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

Bang-bang controlled clock-recovery is widely used in serial link applications as it offers ideal matching between the timing and data samplers and is amenable to fast digital implementation. However, the bang-bang phase detection discards the magnitude information of the timing error and results in inconsistent loop dynamics that vary with the input-noise characteristics. This paper analyzes the jitter-dependent behavior of the tracked oversampling clock-recovery loop, by introducing the concept of effective phase detector gain. Three methods to stabilize the loop bandwidth against jitter variation are described and compared: adapting the loop gain, increasing the oversampling ratio, and adjusting the sampling points. The analyses are then verified with the jitter transfer characteristics obtained from time-step behavioral simulation.

Jitter transfer characteristics of delay-locked loops - theories and design techniques

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a first-order DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase comparator, which enables us to determine an optimal phase-locked loop parameter for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 pspp for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. The results also show that the jitter transfer and jitter tolerance are unaffected by data transition density factors of between 1/8 and 1/2.

Phase dynamics of a timing extraction system based on an optically injection-locked self-oscillating bipolar heterojunction phototransistor

We describe the phase dynamics of a timing extraction system based on direct optical injection locking of a multifrequency oscillator employing an InGaAs/InP heterojunction bipolar phototransistor. We present a general model for the locking range, jitter transfer function, and output phase noise. The model is confirmed by a series of locking experiments. We consider first fundamental timing extraction, that is, a 10-GHz oscillator extracting the clock from a 10-Gbit/s data stream. Second, we address superharmonic timing extraction where 40-Gbit/s data lock the fourth harmonic of the 10-GHz oscillator. In the superharmonic timing extraction case, a clock is extracted at 40 GHz as well as its subharmonics at 10, 20, and 30 GHz.

A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

This paper describes a jitter suppression technique for a 2.48832-Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique decreases the jitter generation and improves the jitter transfer function. Jitter generation is suppressed by boosting the loop gain in the PLL. A suitable jitter transfer function and jitter tolerance is achieved by using a low-center-frequency (f/sub c/) surface acoustic wave (SAW) filter. The fabricated circuit has low jitter generation [about 2.4 mUI rms (below 1 ps rms)] and a low cutoff frequency of the jitter transfer function (about 500 kHz) as a result of using a SAW filter with a f/sub c/ of 622.08 MHz. The jitter generations are within 5 mUI rms (2 ps rms) for the temperature range of 0 to 90/spl deg/. The circuit exceeds the jitter tolerance specifications in the International Telecommunication Union (ITU-T) recommendation G.958 by more than 30%.

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter /spl zeta//spl omega//sub n/ (/spl zeta/ is a damping factor and /spl omega//sub n/ is the natural angular frequency of the PLL), and that the optimization focusing on the /spl omega//sub n/ dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-/spl mu/m Si bipolar technology (f/sub T/ = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers).

On-chip measurement of the jitter transfer function of charge-pump phase-locked loops

An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops (PLLs) is introduced. Input jitter may be generated using one of two methods. Both rely on delta-sigma modulation to shape the unavoidable quantization noise to high frequencies. This noise is filtered by the low-pass characteristic of the device and has little impact on the test results. For an input-output response measurement, the output jitter is compared against a threshold. As the stimulus generation and output analysis circuits are digital, do not require calibration, and demand a small area overhead, this jitter transfer function measurement scheme may be placed on the die to adaptively tune a PLL after fabrication. The technique can also implement built-in self-test (BIST) for the characterization or manufacture test of PLLs. The validity of the scheme was verified experimentally with off-the-shelf components.

Direct digital synthesizer with jittered clock

Since the direct digital synthesizer (DDS) can potentially be used as a flexible clock source, it is of interest to study its spectrum purity as well as jitter characteristic. In this paper, we investigate the jitter transfer characteristic of the DDS clock driven by a jittered digital-to-analog converter (DAC) clock. We first derive the dosed form expressions of the spectrum of the DAC output signal with jittered driving clock. These expressions are then used to investigate the spectral structure of the DDS clock. Equations are derived for the calculation of the SNR. For a small phase noise power in the driving clock, the DDS clock SNR is obtained in a simple closed form and is shown to be lower than that of the input driving clock by the amount of 20 log(f/sub s//d/sub d/) dB, where f/sub s/ is the nominal driving clock frequency and f/sub d/ is the desirable DDS output clock frequency.

A new very fast pull‐in phase‐locked loop with antipseudo‐lock function

AbstractWith the development of high‐speed digital communications, e.g., optical fiber communications, smaller, faster, retiming devices are being required. The phase‐locked loops (PLLs) are suited to an integration compared to surface acoustic wave (SAW) or liquid crystal (LC) passive filters. Therefore, PLLs have been put to use gradually as clock extraction devices in any frequency range over 100 MHz. The authors have developed the previously reported PLL with frequency difference detector (FDD) to provide a new function, which is useful to overcome the pseudo‐lock problem in conventional retiming PLLs and also improved performance of the FDD. The proposed PLL has been constructed with ECL‐IC, PLA and other discrete parts. It has been evaluated experimentally and the PLL designed with a 0.8‐μ design‐rule bipolar transistor has been evaluated by simulation to confirm the following characteristics.1. The PLL can detect an initial unlock state and pseudo‐lock state within almost the same time as FDD sampling time and can recover rapidly.2. The jitter transfer function is almost equal to the usual first‐order PLL and is independent of input data patterns.3. The FDD frequency detecting range, corresponding to the PLL lock‐in range, is more than four times that of the previously proposed FDD‐PLL.

Reduced pull-in time of phase-locked loops using a simple nonlinear phase detector

For a single-loop frequency synthesiser, there is a trade-off between time-to-lock and output phase-noise. To lock a PLL quickly, a high natural frequency ( omegan) is required, while a low omegan is necessary to obtain good jitter damping. The author presents a technique to reduce the time to lock of a frequency synthesiser PLL without changing the jitter transfer function.

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and phase-lock loop (FPLL) to recover a stable clock from pseudo-random non-return-to-zero (NRZ) data. The IC is mounted on a 1-in*1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the synchronous optical network (SONET) OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock has less than 2 degrees rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2 degrees RMS clock jitter. Total current consumption from a single 5.2-V supply is 250 mA.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Accumulation of Jitter: A Stochastic Model

A problem that has been considered extensively in the past is the accumulation of jitter in a chain of regenerative repeaters. For simplicity it is usually assumed that all repeaters in the chain are identical. However, this is not the case in real systems, where considerable differences among the repeaters of a chain have been observed. These random variations are due mainly to manufacturing tolerances, aging effects, temperature changes, etc. In this work, we examine the accumulation of systematic and random jitter along the chain, when the repeater transfer functions are subjected to random variations. We derive expressions for the expected value and variance of the output jitter spectrum in terms of average values of the repeater's jitter transfer function. In addition we find the expected value and the variance of the RMS jitter. Finally we examine two special cases where the timing circuit employs either a phased-locked loop or a surface acoustic wave filter, and derive some asymptotic relations for the power spectral density and root-mean-square value of the accumulated systematic jitter.