Jitter Transfer Research Articles

Analysis of Mueller–Muller Clock and Data Recovery Circuits with a Linearized Model

With the development of high-speed analog-to-digital converter (ADC)-based wireline receivers, the Mueller–Muller clock and data recovery (MM-CDR) circuit has garnered increasing attention. But in the design stage, evaluating the loop performance of MM-CDR circuits in ADC-based wireline receivers is challenging due to the absence of a linearized model for a Mueller–Muller phase detector (MMPD). In this paper, a linearized model of the MMPD is proposed by analyzing the output probability of the MMPD in different transition patterns with random jitter injection, and the model is combined with an entire MM-CDR system to analyze the performance of the MM-CDR loop. Analysis of the linearized model and corresponding simulations indicate that when the reference voltage level in the MMPD is set equal to the amplitude of the average crossing voltage at the intersection of 011 and 110 patterns, the MMPD can obtain the maximum gain, which is determined by jitter, and the jitter transfer function and jitter tolerance can achieve optimum performance.

A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance

The demand for low-power wireline circuits has motivated extensive work on novel circuit solutions. This article describes a one-eighth-rate clock and data recovery (CDR) circuit and a demultiplexer (DMUX) for processing four-level pulse-amplitude modulation (PAM4) signals in receivers (RXs). Detecting both major and minor data transitions, the proposed architecture can achieve a wider loop bandwidth (BW), suppressing oscillator phase noise and improving the jitter tolerance. Fabricated in 28-nm CMOS technology, the prototype provides a jitter transfer BW of 160 MHz with a tolerance of 1 UI at 10 MHz.

Analysis of Pre-Driver and Last-Stage Power-Ground-Induced Jitter at Different PVT Corners.

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct DC supply voltages at the pre-driver (i.e., /) and last stage (i.e., ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

Estimation of Phase Noise Transfer Function

Quantifying frequency converters’ residual phase noise is essential in various applications, including radar systems, high-speed digital communication, or particle accelerators. Multi-input signal source analyzers can perform such measurements out of the box, but the high cost limits their accessibility. Based on an analysis of phase noise transmission theory and the capabilities of popular instrumentation, we propose a technique extending the functionality of single-input devices. The method supplements absolute noise measurements with estimates of the phase noise transfer function (also called the jitter transfer function), allowing the calculation of residual noise. The details of the hardware setup used for the method verification are presented. The injection of single-tone and pseudo-random modulations to the test signal is examined. Optional employment of a spectrum analyzer can reduce the time and number of data needed for characterization. A wideband synthesizer with an integrated voltage-controlled oscillator was investigated using the method. The estimated transfer function matches a white-box model based on synthesizer’s structure and values of loop components. The first results confirm the validity of the proposed technique.

Improved Target Impedance Concept With Jitter Specification

In this article, an improved target impedance concept directly correlating circuit output jitter with power distribution network (PDN) R-L-C parameters is proposed. A systematic procedure to develop the target impedance curves is formulated and developed for common CMOS buffer circuits. The relationship between output jitter and PDN R-L-C parameters is analytically derived by evaluating the time domain voltage ripple to jitter transfer relationship along with the relationship between time domain voltage ripple and PDN R-L-C parameters. Given the transient integrated circuit switching current and the jitter specification, multiple target impedance curves can be defined for a specific circuit. The jitter and PDN R-L-C analytical correlations are validated through HSPICE simulation. The application of the proposed target impedance concept with jitter specification is also demonstrated via simulation.

Analysis of Nonlinear Power Distribution Network and Estimation of Jitter Transfer Functions Based on Output Buffer Pseudo Open Drain Termination

With increasing data rates of links, jitter budget allowable for the channel keeps decreasing, and precisely estimating jitter becomes very important to have confidence in designing a robust communication system. Current analysis of jitter transfer function assumes a linear or approximately linear power distribution network, but the linearity of power distribution network can be distorted by driver states or load conditions at the end of signal channel. In order to estimate power supply induced jitter accurately, both the receiver termination mode and the interconnection parameters of channel should be considered. In this paper, the nonlinearity of power distribution network caused by termination mode and its effect on jitter are discussed. The emphasis is given to the pseudo open drain termination, which is the popular scheme used in DDR4. Then, an analytical calculation method of transfer functions relating power supply noise to jitter is proposed, in which the nonlinear power distribution network model including the output buffers, signal channels, and pseudo open drain terminations is used to derive the analytical expressions. Simulation results demonstrate that the proposed analytical estimation method achieves good agreement with ADS simulated results under a real case power distribution network.

A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

This brief presents an input-data-jitter-tolerant injection-type clock and data recovery (CDR) circuit with a super-harmonic injection-locked ring oscillator (SH-ILRO). Unlike prior injection-type CDRs that utilize a power-hungry CML-type data injection path or for which the data rate is limited to the process-defined CMOS logic bandwidth, the proposed injection-type CDR achieves energy-efficient data edge injection. The proposed wide-bandwidth source follower-based edge detector extracts the input data edge energy efficiently. The proposed SH-ILRO enables quarter-rate injection-locking without high-speed injection selection logic. Fabricated in 65-nm CMOS, the prototype injection-type CDR consumes 19.08 mW at 12 Gb/s with 87-MHz jitter transfer bandwidth and more than 1.0 UIpp jitter tolerance at 20 MHz.

A CDR System Based on Improved Second Order Digital Filter, Hysteretic Voter and Phase Interpolator

The proposed Clock and data recovery system (CDRS) has three improved parts. The second order digital filter with rounding algorithm implements fractional gain and avoids direct current quantization noise which varies between -q/2 and +q/2 while that of traditional filter varies between 0 and +q (q is quantization step). The hysteresis majority voter can combat high frequency and strong jitter especially in quasi-steady state. The improved Phase interpolator (PI) has much smaller current-switching glitch and phase glitch since the weighting current changes gradually instead of steeply. The optimized CDRS can handle up to ±6000ppm (parts per million) frequency offset and the phase resolution is 1.4º/LSB (Least significant bit) according to analysis. The simulations of jitter transfer function and jitter tolerance by Matlab, simulations of phase noise by spectre using Verilog+VeriloA model, and measurements of frequency offset and jitter tolerance all show its good performance.

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

This paper provides an in-depth analysis of the third-order bang-bang clock and data recovery (BBCDR) circuit, which accurately predicts its operating characteristics, namely, the jitter transfer function (JTF), the jitter tolerance (JTOL), and the jitter generation (JGEN). By formulating the time-domain waveforms, we introduce a characterizing method and also derive the closed-form equations and their simplified versions under specific conditions, which are related with the second-order loop filter (LF). Our framework is consistent with the conclusions of the prior works. Also, we discuss through the time-domain behavior, the sinking area of the JTOL and other specific phenomenon appearing in the third-order BBCDR loop. We verify all above prediction by system-level simulations with the MATLAB/simulink model.

Precise Analytical Model of Power Supply Induced Jitter Transfer Function at Inverter Chains

Precise analytical models of power supply noise induced jitter (PSIJ) at inverter chains are proposed. Based on the piecewise linear approximated I–V curve model, analytical models of local PSIJ transfer functions at local rising and falling edges are derived. The total PSIJ transfer function of an inverter chain output is then estimated by alternately accumulating the local PSIJ transfer function at local rising and falling edges. Based on several assumptions, the full PSIJ transfer function model is significantly simplified, which provides physical insights of PSIJ at inverter chains. Accuracy of the proposed analytical model is successfully validated by SPICE simulations with 130 nm CMOS technology. In addition, properties of the PSIJ transfer function at inverter chains are analyzed based on the proposed model.

Analytic Calculation of Jitter Induced by Power and Ground Noise Based on IBIS I/V Curve

Supply fluctuation is one of the most significant factors that cause jitter in high-speed I/O links. The traditional SPICE simulation or measuring method for power supply induced jitter is quite time-consuming and draining on resources. The I/O buffer information specification (IBIS) model is a popular standard for electronic behavioral specifications of digital integrated circuit I/O characteristics. Analytic jitter transfer functions for supply fluctuations are derived by solving two-order differential equations based on IBIS current versus voltage characteristics and pin package parameters. Then, the total time interval error induced by power and ground noise is obtained in both frequency domain and time domain. The method is validated by comparing the analytic calculation results with HSPICE simulated results for a DDR4 output buffer.

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. The proposed automatic frequency acquisition scheme implemented using a conventional bang–bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition density, and is applicable to subrate CDRs. A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs. The CDR is implemented using a digital D/PLL architecture to decouple JTRAN bandwidth from jitter tolerance (JTOL) corner frequency, eliminate jitter peaking, and remove JTRAN dependence on BBPD gain. Fabricated in a 65 nm CMOS process, the prototype CDR achieves error-free operation (BER ${\rm{ ) from 4 to 10.5 Gb/s with pseudorandom binary sequence (PRBS) data sequences ranging from PRBS7 to PRBS31. The proposed automatic frequency acquisition scheme always locks the CDR loop within 1000 ppm residual frequency error in worst case. At 10 Gb/s, the CDR consumes 22.5 ${\rm{\,mW}}$ power and achieves a recovered clock long-term jitter of 2.2 ${\rm ps_{rms}}$ /24.0 ${\rm{ ps_{pp}}}$ with PRBS31 input data. The measured JTRAN bandwidth and JTOL corner frequencies are 0.2 and 9 MHz, respectively.

Clock and Data Recovery for 10-Gb/s EPON Application

An integrated 10-Gb/s clock and data recovery circuit incorporates a LC-tank voltage-controlled oscillator, a half-rate binary phase detector and charge pump. On the basis of R.C.Walker's second-order model, and in accordance with jitter tolerance and jitter transfer, the minimum stability factor are derived in a view to determine the value of Cz and Rz finally. Accomplished circuit design in 0.13-um CMOS process, the power consumption is 210 mW from a supply voltage of 1.2V. When 10.125 Gb/s pseudorandom binary sequence is used, the jitter of the recovered clock is a peak-to- peak jitter of 8 ps.

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links

A full-rate burst-mode receiver that achieves fast on/off operation needed for energy-proportional links is presented. By injecting input data edges into the oscillator embedded in a classical Type-II digital clock and data recovery (CDR) circuit, the proposed receiver achieves instantaneous phase-locking and input jitter filtering simultaneously. In other words, the proposed CDR combines the advantages of conventional feed-forward and feedback architectures to achieve energy-proportional operation. By controlling the number of data edges injected into the oscillator, both the jitter transfer bandwidth and the jitter tolerance corner are accurately controlled. The feedback loop also corrects for any frequency error and helps improve CDR's immunity to oscillator frequency drift during the power-on and -off states. This also improves CDR's tolerance to consecutive identical digits present in the input data. Fabricated in a 90 nm CMOS process, the prototype receiver instantaneously locks onto the very first data edge and consumes 6.1 mW at 2.2 Gb/s. Owing to its short power-on time, the receiver's energy efficiency varies only from 2.77 pJ/bit to 3.87 pJ/bit when the effective data rate is varied from 0.44 Gb/s to 2.2 Gb/s. Input sensitivity of the receiver is 36 mV for a BER of 10 -12 .

An all-digital semi-blind clock and data recovery system

This paper presents a digitally intensive semi-blind clock and data recovery (SBCDR) system. The paper covers the theory, analysis, and system level simulation of this SBCDR. The proposed CDR is tailored to target the optical network standard OC-192. The SBCDR can provide the required jitter tolerance (JTo), and still provide enough jitter filtering to achieve the jitter transfer (JTr) requirements. Also, the recovered clock achieves a low jitter generation (JG) of 0.01 UIrms and 0.0064 UIrms for both the wide-band and high-band jitter filters defined by the standard. The proposed SBCDR provides two advantages over typical SBCDRs and PLL-based CRDs that target OC-192. First, the digitally intensive nature provides a scalable and process tolerant design. Second, the architecture provides a CDR that can pass all three jitter performance metrics, without the aid of an external clean-up phase locked loop (PLL) or a high performance clock multiplication unit (CMU) typically required by OC-192 transceivers. By utilizing a circular representation for the phase calculation in the over-sampling clock and data recovery (OSCDR), extensive pipe-lining in the implementation and higher data rate tolerance can be achieved. The simulation results of the proposed SBCRD agree closely with theoretical results.

DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELAY LOCKED LOOP USING SC FILTER

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz and Q=500 provides very low cut off frequency.

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously reported peaking-free PLLs require additional circuit components which may adversely affect clock jitter or increase hardware complexity, the presented PLL requires only a new type of digital loop filter. The analysis on the loop dynamics and design of the optimal loop filter are presented. As for the implementation, a low-power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency detectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpolators. A digitally controlled oscillator (DCO) is implemented as a transformer-tuned LC oscillator whose frequency is set by a ratio between two digitally controlled currents. The digital PLL prototype, fabricated in a 65 nm CMOS, demonstrates 1.2 ps rms integrated jitter at 9.2 GHz and 1.58 μs settling time with 700 kHz bandwidth while dissipating 63.9 mW at a 1.2 V nominal supply.

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop

A reference-less half-rate digital clock and data recovery (CDR) circuit employing a phase-rotating phase-locked loop (PRPLL) as phase interpolator is presented. By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain. Fabricated in a 90 nm CMOS process, the prototype CDR achieves error-free operation (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) with PRBS data sequences ranging from PRBS7 to PRBS31. At 5 Gb/s, it consumes 13.1 mW power and achieves a recovered clock long-term jitter of 5.0 ps rms/44.0 ps pp when operating with PRBS31 input data. The measured JTRAN bandwidth is 2 MHz and JTOL corner frequency is 16 MHz. The CDR is tolerant to 110 mV pp of sinusoidal noise on the DCO supply voltage at the worst case noise frequency of 7 MHz. At 2.5 GHz, the PRPLL consumes 2.9 mW and achieves -134 dBc/Hz phase noise at 1 MHz frequency offset. The differential and integral non-linearity of its digital-to-phase transfer characteristic are within ±0.2 LSB and ±0.4 LSB, respectively.

A novel approach to analysis and design of bang-bang CDR circuits

Purpose – Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized. The paper aims to discuss these issues. Design/methodology/approach – The presented method is general enough to be used for designing the BBCDR loop parameters to meet SONET jitter transfer requirements (loop bandwidth and jitter peaking). Findings – In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized by formulating the time domain waveforms. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The validity of the resulted equations is verified through HSPICE simulations using TSMC 0.18-μm CMOS process. Simulation results show that good conformance between analytical equations and simulation results. Originality/value – The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero. The presented method is general enough to be used for designing the BBCDR.

Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits

This paper describes an accurate, yet analytical method to predict the key characteristics of a bang-bang controlled timing loop: namely, the jitter transfer (JTRAN), jitter generation (JG), and jitter tolerance (JTOL). The analysis basically derives a linearized model of the system, where the bang-bang phase detector is modeled as a set of two linearized gain elements and an additive white noise source. This phase detector (PD) model is by far the most extensive one in literature, which can correctly estimate the effects of random jitter, transition density, and finite loop latency on the loop characteristics. The described pseudo-linear analysis assumes the presence of random jitter at the PD input and the minimum jitter necessary to keep the linear model valid is derived, based on a describing function analysis and Nyquist stability analysis. The presented analysis re-confirms the findings of prior theories and provides theoretical basis to the prior empirically-drawn equations, such as those for the quantization noise power and the gain reduction in presence of a finite loop delay. The predictions based on the presented analysis match well with the results from time-accurate behavioral simulations.