Jitter Simulations Research Articles

Yield Enhancement of Face-to-Face Cu–Cu Bonding With Dual-Mode Transceivers in 3DICs

When more than one dies are stacked vertically in 3-D integrated circuits (3DICs), the overall system yield degrades significantly. While each die can be tested before stacking, failures in 3DIC interconnects could jeopardize the entire system. In this paper, a dual-mode transceiver is proposed as a built-in-self-test/repair solution to improve the yield of direct face-to-face copper thermocompression bonding (Cu–Cu bonding). The proposed transceiver could improve the Cu–Cu bonding-based interconnect reliability with the introduction of two operation modes: the ohmic mode when Cu–Cu bonding presents low resistance and the capacitive coupling mode when Cu–Cu bonding is showing any sign of failure with high resistance at the bonding interface. Such mode sensing is self-contained in the transceiver itself with the help of the proposed resistance sensor. In this paper, we discuss the modeling of Cu–Cu bonding and the proposed transceiver design with power, latency, jitter, and crosstalk simulations followed by the design guideline for the practical implementation with yield analysis.

A novel tracking jitter computation method for delay‐locked loops in spread‐spectrum systems

ABSTRACTIn spread‐spectrum navigation systems, the positioning error (or tracking accuracy) is determined from the jitter deviation of delay‐locked loops (DLLs). However, jitter simulations are computationally complex, and conventional analytical methods provide only unsatisfactory and incomplete jitter results. Thus, our contribution presents a novel method for the analytical jitter computation by mapping the stochastic differential equation (SDE) of the DLL onto an Ornstein–Uhlenbeck (OU) SDE. Its solution is the well‐known OU random process, which is a time‐variant Gaussian distribution. The expectation value and the variance of the OU random process yield the jitter deviation. Thus, we derive the analytical time‐variant jitter function with its transient response, which was to date unavailable. Contrary to previous jitter computations based on a loop transfer function, our method covers DLLs of any order. We obtain the loop parameters that minimise the jitter deviation analytically without computationally complex simulations. Above all, our method based on OU random processes enables for the first time an efficient joint analytical mean time to lose lock (MTLL) and jitter computation. Therefore, both computationally complex MTLL and jitter simulations become obsolete for many kinds of DLLs.Copyright © 2012 John Wiley & Sons, Ltd.

The impact of ‘phase’ measurement on waiting time jitter simulations

Clock rate adaptation is usually used in synchronizing different data streams in digital networks. Although, clock rate adaptation provides timing transparency for various data tributaries, it inherently produces a low-frequency timing jitter which is known as the waiting time jitter. The properties of waiting time jitter are discussed in detail in this paper. In particular, a basis for the analysis, simulation and modelling of the waiting time jitter is provided by clearly identifying the necessary approximations. An accurate simulation model of the synchronizer that is suitable for studying the waiting time jitter is developed. The developed model is used to provide an assessment of the performance of popular ‘threshold modulation’ type jitter reduction techniques.