Jitter Generation Research Articles

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The proto-type digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) for PRBS data sequences ranging from 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> - 1 to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.

Optical disc jitter generator and its calibration system

Jitter is one of the most important parameters for optical disc evaluation. This paper presents a design of a simulated optical disc jitter generator based on a sinusoidal frequency-modulated (FM) signal. An innovative method is proposed to calibrate the jitter generator based on the Bessel-zero method. Finally, measurement uncertainty of the calibration system is described. The results of theoretical analysis and experiments indicate that the expanded uncertainty of measurement is 0.13% in CD mode, and 0.18% in DVD mode, k = 2.

Stochastic interpolation model of the medial superior olive neural circuit

This article presents a stochastic model of binaural hearing in the medial superior olive (MSO) circuit. This model is a variant of the slope encoding models. First, a general framework is developed describing the elementary neural operations realized on spike trains in individual parts of the circuit and how the neurons converging onto the MSO are connected. Random delay, coincidence detection of spikes, divergence and convergence of spike trains are operations implemented by the following modules: spike generator, jitter generator, and coincidence detector. Subsequent processing of spike trains computes the sound azimuth in the circuit. The circuit parameters that influence efficiency of slope encoding are studied. In order to measure the overall circuit performance the concept of an ideal observer is used instead of a detailed model of higher relays in the auditory pathway. This makes it possible to bridge the gap between psychophysical observations in humans and recordings taken of small rodents. Most of the results are obtained through numerical simulations of the model.

Parametric analysis with micro jitter generation for a direct current charging roller based electrophotographic device

To realize high quality electrophotography, it is important to clarify the influence of the design parameters in a charging roller (CR) system on the output image on the paper. We first analyzed the parameters related to the direct current (dc) bias CR system, and consequently confirmed micro jitter generation as a printing quality indicator for varying CR resistance and the surface roughness of the CR elastic layer. It turned out that the micro jitters were correspondingly generated for the chosen representative parameters, and therefore, the analyses can be used as a design platform to prepare an optimum dc CR system.

A Simple Method of Jitter Evaluation for Designing Phase-Locked Loops for Optical Communication Systems

A simple method for evaluating jitter generation is proposed for phase-locked loops (PLLs) applied to optical communication systems. The precise but complex expressions in the conventional method involving the phase noise of the voltage-controlled oscillator, the jitter-transfer function of the PLL, and integration using a filter function are greatly simplified with the objective of providing a simple estimate of the jitter generation avoiding iterative design procedures. These simplifications together with the data from the International Telecommunication Union (ITU)-T Recommendations lead to an integral-free expression with only a small number of parameters, which enables jitter evaluation using a hand-held calculator. By applying bandwidth limits to the jitter tolerance and transfer specifications, both the sufficient and insufficient conditions for the phase noise of a voltage-controlled oscillator are obtained to enable the efficient design of a PLL with the jitter generation specified in the ITU-T Recommendations.

Watching the brain oscillating : A neural correlate of illusory jitter

Moving borders defined by small luminance changes (or by colour changes), placed in close proximity to moving borders defined by large luminance changes, can appear to jitter at a characteristic frequency (Arnold & Johnston, 2003). To reveal the neurophysiological substrates of this illusion we measured brain activity using magnetoenceohalography (MEG). In conditions 1–3, vertical green bars, superimposed upon larger red squares, moved across a black background. The green bars were either (1) darker, (2) isoluminant with, or (3) brighter than the red squares. In condition 4, vertical green bars moved across an isoluminant red background. In condition 5, physical jitter was added to dark green bars centered in a moving red square to mimic illusory jitter. In conditions 1-4, subjects indicated if the green bar appeared to jitter. If illusory jitter was reported, subjects then matched the illusory jitter rate to the frequency of an adjacent physical jitter. The matched frequency for each subject was used in condition 5. Illusory jitter was only perceived in condition 2 and its frequency was ~10 Hz. We also found that neural oscillations around 10 Hz were significantly enhanced in condition 2 relative to all other conditions. As these oscillations were enhanced relative to isoluminant motion (condition 4) and physical 10 Hz jitter (condition 5), we believe that the enhanced activity is related to illusory jitter generation rather than to jitter perception or to isoluminant motion per se, supporting our hypothesis that MISC is generated within cortex by a dynamic cortical feedback circuit.

Study of Subharmonically Injection-Locked PLLs

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon. It explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue. All of the analyses are verified by real chip measurements. Two 20-GHz PLLs based on the proposed theory are designed and fabricated in 90-nm CMOS technology to demonstrate the superiority and robustness of this technique. The first chip aims at low-noise/low-power/high-divide-ratio design, achieving 149-fs rms jitter (integrated from 100 Hz to 1 GHz) while consuming 38 mW from a 1.3-V supply. The second prototype shoots for the lowest noise performance, presenting 85-fs rms jitter (the same integration interval) with a power dissipation of 105 mW. The jitter generation (from 50 kHz to 80 MHz) measures 48 fs, which is at least twice as small as that of any other known circuits. </para>

Line Codes for Clock Recovery with Low-Q Filtering

The principles of multiple block code (MBC) that feature in filter-less clock recovery are overviewed. Jitter generations are discussed to show that reducing the total amount of delay in MBC family coding can lead to suppressing jitter generation. Jitter accumulation in the repeater chain is also discussed to show that applying very low-Q filtering can drastically reduce the accumulation of high-frequency jitter. New members of MBC family codes for clock recovery with low-Q filtering that can reduce the total amount of delay in coding by a factor of six at the most are proposed. It is confirmed in an experimental set up that pattern dependent jitter can be reduced by a factor of three. An extended version of family members that can improve coding efficiency are proposed and confirmed in an experimental set up.

Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation

In the last few years, several digital implementations of phase-locked loops (PLLs) have emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang phase detector to convert the phase error into a digital value. Unfortunately, that introduces a hard nonlinearity in the loop which prevents the use of the traditional linear analysis. Nevertheless, authors resort to linearized models for the noise analysis of this kind of loops, but to the author's knowledge, no attempt has been made to evaluate the limits of this approach. In this paper, we address the problem of investigating the limits of the linearized approach, and we apply it to the computation of the jitter transfer and the jitter generation depending on the level of noise at the binary phase detector input. The results will be compared to phase noise measurements obtained from a digital bang-bang PLL implemented in 130-nm CMOS technology.

Alpha band amplification during illusory jitter perception

Synchronization is thought to have a role in linking disparate components into neural assemblies. However, the particular frequency of the synchronization is generally considered to be incidental to its functional role. Here we report a link between enhanced alpha activations and an illusory jitter of the same frequency. We measured perceived jitter rates and the magnetoencephalography during presentations of a stimulus wherein red squares and superimposed vertical green bars moved together across a black background. The green bars were either darker, equiluminant with, or brighter than the red squares. We established that the illusory jitter rate, robustly seen only in the equiluminant condition, was approximately 10 Hz. Crucially, neural oscillations around 10 Hz were enhanced in this condition. Surprisingly, approximately 10 Hz oscillations were also enhanced during illusory jitter perception relative to a moving stimulus that contained physical 10 Hz jitter. This suggests that the enhanced synchronization is associated with illusory jitter generation rather than with jitter perception. Since the stimulus eliciting illusory jitter moves smoothly and rigidly, both the percept and enhanced neural synchrony must be generated within the visual system. Our data therefore indicate a match between the dynamics of synchronous neural activity and the dynamics of a sensory experience offering the intriguing possibility of a common cause.

Modeling of Eye-Diagram Distortion and Data-Dependent Jitter in Meander Delay Lines on High-Speed Printed Circuit Boards (PCBs) Based on a Time-Domain Even-Mode and Odd-Mode Analysis

Crosstalk induced in a meander delay line produces a significant amount of waveform distortion and data-dependent jitter at the output port. This paper introduces an interpretation of the eye-diagram distortion and the jitter generation mechanism based on a time-domain even- and odd-mode analysis of a coupled transmission line structure. From the proposed analysis, this paper proposes jitter-estimation equations for both the short and long unit line delay cases. The eye-diagram distortion and timing jitter are predicted and estimated, respectively. In order to verify the jitter-estimation equations, a series of microstrip-type printed circuit board test vehicles with the meander delay line are fabricated and tested. The measured jitter shows good agreement with the proposed jitter-estimation equations.

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

A novel topology of phase detector (PD) for applications in clock recovery systems from nonreturn-to-zero data is presented in this paper. The PD operates directly on the data stream, without requiring preprocessing, and behaves like a sampling-type PD, providing a sinusoidal phase characteristic. The triple-tail cell principle is exploited to obtain a circuit topology suitable to low-voltage high-speed applications, with a very simple structure and thus limited jitter generation. A model is proposed to understand circuit behavior and optimize its design. The PD has been used in a clock-and-data recovery circuit for 10-Gb/s optical communications, and measurements in agreement with SONET specifications are reported.

Improvement of jitter transfer characteristics of a 9.95328 Gb/s data recovery DLL using saw filter

This paper presents a design of a high-speed data recovery circuit for non return zero (NRZ) data transmission using delay-locked loop (DLL) with SAW filter. The jitter generation of the circuit is decreased by adjusting the loop gain in DLL whereas surface acoustic wave (SAW) filter with low centered frequency ( f c) improves the jitter transfer function of DLL. It is seen that the circuit using SAW filter of f c = 1.24416 GHz and Q = 1000 provides the cut off frequency of about 600 kHz which is ∼10 times lower than that of conventional DLL circuit.

A 43-Gb/s full-rate clock transmitter in 0.18-/spl mu/m SiGe BiCMOS technology

A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120 GHz f/sub T/ and 100 GHz f/sub max/ HBTs. It consists of a 4:1 multiplexer, a clock multiplier unit, and a frequency lock detector. The IC features clock jitter generation of 260 fs rms and dissipates 2.3 W from a -3.6-V supply voltage. Measurement results are compared to a previously reported half-rate clock transmitter designed using the same technology.

A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs

This paper describes a 2.5-3.125-Gb/s quad transceiver with second-order analog delay-locked loop (DLL)-based clock and data recovery (CDR) circuits. A phase-locked loop (PLL) is shared between receive (RX) and transmit (TX) chains. On each RX channel, an amplifier with user-programmable input equalization precedes the CDR. Retimed data then goes to an 1:8/1:10 deserializer. On the TX side, parallel data is serialized into a high-speed bitstream with an 8:1/10:1 multiplexer. The serial data is introduced off-chip through a high-speed CML buffer having single-tap pre-emphasis. Proposed DLL-based CDR can tolerate large frequency offsets with no jitter tolerance degradation due to its second-order PLL-like nature. Also, this study introduces an improved charge-pump and an improved phase-interpolator. Fabricated in a 0.15-/spl mu/m CMOS process, the 1.9-mm/sup 2/ transceiver front-end operates from a single 1.2-V supply and consumes 65-mW/channel of which 32 mW is due to the CDR. CDR jitter generation and high-frequency jitter tolerance are 5.9 ps-rms and 0.5 UI, respectively, for 3.125 Gb/s, 2/sup 23/-1 PRBS input data with 800-ppm frequency offset.

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-/spl mu/m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.

Analysis and modeling of bang-bang clock and data recovery circuits

A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the limited pull-in range, and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.

A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems

A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120-GHz f/sub T/ and 100 GHz f/sub max/. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10/sup -9/ is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a -3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a -3.6-V supply voltage.