Iterative Timing Recovery Research Articles

Efficient Iterative Timing Recovery of Low-Density Parity-Check Decoding Metrics Using the Steepest Descent Algorithm for Satellite Communications at Low SNRs

An efficient iterative timing recovery via steepest descent of low-density parity-check (LDPC) decoding metrics is presented. In the proposed algorithm, a more accurate symbol timing synchronization is achieved at a low signal-to-noise (SNR) without any pilot symbol by maximizing the sum of the square of all soft metrics in LDPC decoding. The principle of the above-proposed algorithm is analyzed theoretically with the evolution trend of the probability mean of the soft LDPC decoding metrics by the Gaussian approximation. In addition, an efficiently approximate gradient descent algorithm is adopted to obtain excellent timing recovery with rather low complexity and global convergence. Finally, a complete timing recovery is accomplished where the proposed scheme performs fine timing capture, followed by a traditional Mueller–Müller (M&M) timing recovery, which acquires timing track. Using the proposed iterative timing recovery method, the simulation results indicate that the performance of the LDPC coded binary phase shift keying (BPSK) scheme with rather large timing errors is just within 0.1 dB of the ideal code performance at the cost of some rational computation and storage. Therefore, the proposed iterative timing recovery can be efficiently applied on occasions of the weak signal timing synchronization in satellite communications and so on.

Reduced complexity per-survivor iterative timing recovery using max-log-MAP algorithm

In this paper, we propose a reduced complexity (RC) per-survivor-processing (RC-PSP) iterative timing recovery scheme. The objective is to lessen the computational burden while approaching the optimal system performance of the existing full-complexity (FC) log-MAP (FC-PSP) iterative recovery scheme. This is achieved by utilising the max-log-MAP framework, which converts the multiplications and additions to maximum operations. According to Spasov, Gushev and Ristov, such framework consumes less power, reduces space on a chip and increases decoding speed. Robertson et al. showed that max-log-MAP PSP requires only 5 × 2M − 2 max operations, 10 × 2M additions and 8 multiplications by ±1. Furthermore, it offers a direct mathematical framework for converting the log-MAP-based PSP to max-log-MAP-based PSP for timing recovery. The simulations show that the proposed method outperforms the previous methods. The computational complexity for the max-log-MAP PSP is significantly reduced at the cost of a small bit error rate (BER) performance loss.

Reduced complexity per-survivor iterative timing recovery using max-log-MAP algorithm

In this paper, we propose a reduced complexity (RC) per-survivor-processing (RC-PSP) iterative timing recovery scheme. The objective is to lessen the computational burden while approaching the optimal system performance of the existing full-complexity (FC) log-MAP (FC-PSP) iterative recovery scheme. This is achieved by utilising the max-log-MAP framework, which converts the multiplications and additions to maximum operations. According to Spasov, Gushev and Ristov, such framework consumes less power, reduces space on a chip and increases decoding speed. Robertson et al. showed that max-log-MAP PSP requires only 5 × 2M − 2 max operations, 10 × 2M additions and 8 multiplications by ±1. Furthermore, it offers a direct mathematical framework for converting the log-MAP-based PSP to max-log-MAP-based PSP for timing recovery. The simulations show that the proposed method outperforms the previous methods. The computational complexity for the max-log-MAP PSP is significantly reduced at the cost of a small bit error rate (BER) performance loss.

A Study of Timing Recovery for High-Recording-Density Tape Systems

Today's tape storage systems are widely used as a low-cost solution for data backup and archiving for the rapidly growing amount of digital information produced in various fields. Following the Information Storage Industry Consortium (INSIC) Roadmap [1], tape cartridge capacity continues to scale by doubling the capacity every two years. Developments in read channel technology are expected to play an important role in improving data-storage capability. The introduction of powerful error-correction codes, such as low density parity check (LDPC) codes to the tape storage system (and which have already been applied to current HDD systems) is anticipated to achieve system operation under low SNR conditions, enabling additional increases in areal recording density. However, at a low SNR, a loss-of-lock (LOL) in the phase-locked loop (PLL) will frequently occur in the current timing recovery scheme. Previous studies of the iterative timing recovery scheme [2], [3] enable systems to operate robustly even at low SNR conditions. However, due to the complexity of these systems, the cost of hardware makes it difficult to introduce iterative timing recovery schemes into multichannel tape systems. In this work, it is shown that erroneous feedback in the PLL caused by misdetection of the detector is the major cause for LOL in tape systems at high recording densities. To cope with these misdetections of the detector while maintaining an acceptable latency in the feedback loop, a new timing recovery scheme that utilizes the soft-output information of the detector was studied. The results show that LOL rate performance can clearly be improved by such schemes, with only a small increase in implementation complexity.

Cycle Slip Detection and Correction Through Classification of Modulation Code Failures

In high-density recording systems, synchronization might be lost due to increased noise and/or inaccurate sampling/filtering. In such, long bursts of errors occur due to bits either erased from or inserted into the bit stream. At low signal-to-noise ratios, such bit slips (also known as cycle slips) lead to excessive post-error correction code (post-ECC) failures. In order to reduce the rate of the post-ECC failures, cycle slips should be detected and corrected. In the past, the majority of the research was concentrated on iterative joint timing recovery and error decoding methodologies. In this study, we propose to detect and correct cycle slips using a decoding failure analysis of maximum transition run (MTR) codeword sequences in conjunction with a general-purpose classification algorithm. First, noncyclic properties of constrained coding are identified by realizing that MTR codewords render invalid more often if bit shifts happen. Later, we present a method to use such invalid codewords to help detect and correct cycle slips. Finally, some numerical results are presented to show the effectiveness of the proposed detection/correction scheme using MTR codes and the support vector machines. It is demonstrated that such a combination has the potential for BER and post-ECC failure rate performance improvements by eliminating cycle slips for the generalized partial response channels.

Iterative Timing Recovery with the Split-Preamble Strategy for Coded Partial Response Channels

This paper proposes a modified per-survivor iterative timing recovery scheme, which exploits a new split-preamble strategy in conjunction with a per-survivor processing soft-output Viterbi algorithm (PSP-SOVA). The conventional split-preamble strategy places a preamble at the beginning of a data sector and uses it to run a phase-locked loop during acquisition to find an initial phase/frequency offset. However, the proposed scheme splits the preamble into two parts. The first part is placed at the beginning of the data sector, whereas the second part is divided into small clusters, each of which is then embedded uniformly within the data stream. This split preamble is utilized to adjust the branch metric calculation in PSP-SOVA to ensure that the survivor path occurs in a correct direction. Results indicate that the proposed scheme yields a better performance than a conventional receiver with separate timing recovery and turbo equalization, and the iterative timing recovery scheme proposed in [1],[2], especially when the timing jitter is large. In addition, we also show that the proposed scheme can automatically correct a cycle slip much more efficiently than the others.

Iterative timing recovery via soft decision metrics of low-density parity-check decoding

An efficient scheme for iterative timing recovery via soft decision metrics (SDMs) of low-density parity-check (LDPC) decoding is presented. This scheme employs new metrics from LDPC decoding to overcome the difficult problem of timing synchronisation at low signal-to-noise ratios. It also obtains accurate timing acquisition with a search window-aided Nelder–Mead simplex algorithm by maximising the sum of the absolute values of the SDMs. The whole scheme is implemented, and our algorithm is concatenated with the Mueller–Müller algorithm, which performs timing tracking with LDPC decoding feedback. Our scheme has global convergence, moderate complexity and good performance. The simulation results indicate that the performance of the LDPC-coded binary phase shift keying system with rather large timing errors is within 0.1 dB of the ideal code performance at the cost of some computation and storage resources.

Discrete Polyphase Matched Filtering-based Soft Timing Estimation for Mobile Wireless Systems

In this paper we present a soft timing phase estimation (STPE) method for wireless mobile receivers operating in low signal to noise ratios (SNRs). Discrete Polyphase Matched (DPM) filters, a Log-maximum a posterior probability (MAP) and/or a Soft-output Viterbi algorithm (SOVA) are combined to derive a new timing recovery (TR) scheme. We apply this scheme to wireless cellular communication system model that comprises of a raised cosine filter (RCF), a bit-interleaved turbo-coded multi-level modulation (BITMM) scheme and the channel is assumed to be memory-less. Furthermore, no clock signals are transmitted to the receiver contrary to the classical data aided (DA) models. This new model ensures that both the bandwidth and power of the communication system is conserved. However, the computational complexity of ideal turbo synchronization is increased by 50%. Several simulation tests on bit error rate (BER) and block error rate (BLER) versus low SNR reveal that the proposed iterative soft timing recovery (ISTR) scheme outperforms the conventional schemes.

Iterative symbol timing recovery for short burst transmission schemes

This paper presents a novel iterative symbol timing recovery (STR) scheme for short burst transmission formats, a paradigm commonly found in modern wireless systems, like, for instance, time division multiple access (TDMA) schemes and future wireless packet data networks. Both data-aided (DA) and decision-directed (DD) solutions are considered and performance is pursued by means of an iterative burst-by-burst scheme which exploits the Farrow structure for the polynomial interpolation filter. The convergence of the algorithm is discussed according to the expectation maximization (EM) framework. Performance is evaluated by simulating 4-QAM and 16-QAM transceivers and simulations results are compared under different modulation orders and channel conditions, for both the decision-directed and data-aided cases.

Iterative APPA Symbol Timing Recovery for Turbo-coded Systems

This paper examines the problem of symbol timing recovery and decoding in turbo-coded systems. The large coding gain of Turbo-codes enables reliable communications at very low signal-to-noise ratio (SNR). However, the application of turbo coding exacerbates the problem of timing recovery due to its very low operating SNRs. Therefore we propose a new concept: ‘a-priori probability aided’ symbol timing recovery, which is suited to coding systems employing iterative soft-in/soft-out (SISO) decoding such as Turbo Codes, where the log-likelihood ratio obtained from a Maximum A Posteriori (MAP) decoder (as used in turbodecoding) is used to aid estimation in an iterative synchroniser/decoder. This method jointly solves the timing recovery and decoding problem and the synchroniser has effectively no acquisition period. We illustrate this in detail in a turbo-coded BPSK system on AWGN channel. We analyse the performance of the estimator in terms of the mean and the variance of the timing estimate, and demonstrate a substantial performance advantage over conventional non-data-aided (NDA) method. It is also shown that this method can approach the performance of Data-Aided (DA) method without using additional pilot symbols.

Iterative timing recovery

The last decade has seen the development of iteratively decodable error-control codes of unprecedented power, whose large coding gains enable reliable communication at very low signal-to-noise ratio (SNR). A by-product of this trend is that timing recovery must be performed at an SNR lower than ever before. Conventional timing recovery ignores the presence or error-control coding and thus doomed to fail when the SNR is low enough. This article describes the iterative timing recovery, a method for implementing timing recovery in cooperation with iterative error-control decoding so as to approximate a more complicated receiver that jointly solves the timing recovery and decoding problems.

Cycle-slip-detector-aided iterative timing recovery

The latest developments in low-density parity-check codes have shown performances very close to the channel capacity. However, in order to use these capacity-approaching codes in the magnetic recording channel, the cycle-slip problem in the synchronizer has to be solved. In this paper, we develop a cycle-slip detector (CSD) for the binary intersymbol interference channel that uses the channel soft-output information as its input. This CSD is then used in an iterative timing recovery scheme to eliminate cycle slips. Our simulation results show that utilizing the CSD improves the convergence speed of iterative timing recovery.

Complexity Reduction of Modied Per-Survivor Iterative Timing Recovery for Partial Response Channels

The problem of timing recovery operating at low signal-to-noise ratio has been recently solved by a modified per-survivor iterative timing recovery (MPS-ITR) proposed in [1], which jointly performs timing recovery, equalization, and error-correction decoding. In practice, this scheme exploits a splitpreamble strategy in conjunction with a per-survivor soft-output Viterbi algorithm equalizer to make it more robust against severe timing jitters or cycle slips. Although the MPS-ITR outperforms existing iterative timing recovery schemes [1], its complexity is extremely high. Therefore, this paper proposes a reduced-complexity MPS-ITR scheme (denoted as MPS-ITR-M) to make it more implementable in reallife applications. This is achieved by applying the M-algorithm [2] to the MPS-ITR. Numerical results show that at low-to-moderate complexity, the MPSITR- M performs better than other schemes.