Iterative Decoding Algorithm Research Articles

Mitigating ambient noise and multi-path propagation in underwater communication using the DSTTD-OFDM system

We consider turbo coded multi-carrier double space–time transmit diversity (DSTTD) system that employs orthogonal frequency division multiplexing (OFDM) for the transmission of acoustic signals in underwater communication, where acoustic interference and ambient noise are the major channel deficiencies. DSTTD employs two space–time block codes at the transmitter. At each receiver, we implement space–time Block-Nulling detection technique to increase throughput. We consider the iterative decoding algorithm at the receiver to alleviate the effects of ambient noise and acoustic interference. Further, we implement multi-carrier modulation technique to mitigate the effects of multipath propagation. We investigate the effects of eleven tap delay pertaining to shallow water channel model for the DSTTD-OFDM system. Our simulation results reveal that our considered system with Block-Nulling technique provides better bit error rates for lower signal-to-noise ratio when compared to a minimum mean square error detector-based system. Further, it achieves higher throughput with fewer computations at the receivers.

Soft decoding method for systematic raptor codes

Raptor codes are a class of rateless codes that were originally designed for binary erasure channels. To enhance their performance, multiple soft iterative loops can be employed in the decoder. In this study, the authors propose a method to construct modified Tanner graphs for systematic raptor codes in order to increase the efficiency of soft decoding. A modified Tanner graph is drawn in terms of bit and check nodes for each component code, instead of encoding and information nodes, as in conventional Tanner graphs, for its component Luby transform codes. This modified Tanner graph enables the use of a more simplified soft iterative decoding algorithm and provides improved decoding performance compared with the conventional method. In addition, they propose an efficient joint iterative soft decoding method with a parallel process to speed up the iterative decoding. The simulation results in this study reveal that the modified Tanner graph works better than the conventional Tanner graph for joint iterative decoding, and that the proposed parallel decoding method can contribute to further enhance the performance as well as the decoding speed by reducing the average number of iterations.

FPGA implementation of low complexity LDPC iterative decoder

ABSTRACTLow-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.

Comparative study of LDPC coding schemes and FPGA implementation for inter‐vehicle communications

A novel comparative study of different low-density parity-check (LDPC) coding algorithms and implementation issues through field-programmable gate arrays (FPGAs) technology for wireless vehicular applications is presented. A key development in LDPC codes is the iterative decoding algorithm which uses the belief propagation algorithm. A comprehensive investigation of the performance of different coding schemes was carried out. Four different decoding techniques were tested by computer-based simulations of messages modulated under the binary phase-shift keying modulation scheme and transmitted through a vehicular channel model. Finally, the best performance ratio against complexity algorithm was chosen to be implemented on a Xilinx FPGA platform.

Block Markov Superposition Transmission: Construction of Big Convolutional Codes From Short Codes

A construction of big convolutional codes from short codes called block Markov superposition transmission (BMST) is proposed. The BMST is very similar to superposition block Markov encoding (SBME), which has been widely used to prove multiuser coding theorems. The BMST codes can also be viewed as a class of spatially coupled codes, where the generator matrices of the involved short codes (referred to as basic codes) are coupled. The encoding process of BMST can be as fast as that of the basic code, while the decoding process can be implemented as an iterative sliding-window decoding algorithm with a tunable delay. More importantly, the performance of BMST can be simply lower bounded in terms of the transmission memory given that the performance of the short code is available. Numerical results show that: 1) the lower bounds can be matched with a moderate decoding delay in the low bit-error-rate (BER) region, implying that the iterative sliding-window decoding algorithm is near optimal; 2) BMST with repetition codes and single parity-check codes can approach the Shannon limit within 0.5 dB at the BER of $10^{-5}$ for a wide range of code rates; and 3) BMST can also be applied to nonlinear codes.

A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders

Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are $\alpha$ and $\beta$ recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing. In this brief, a novel relation existing between the $\alpha$ and $\beta$ metrics is introduced, leading to a novel add–compare–select (ACS) architecture. The proposed technique can be applied to both the precise approximation of log-MAP and max-log-MAP ACS architectures. The proposed ACS design, which is implemented in a 0.13- $\mu\mbox{m} $ CMOS technology and customized for the LTE standard, results in, at most, 18.1% less area compared with the reported designs to date while maintaining the same throughput level.

Reliability-based iterative proportionality-logic decoding of LDPC codes with adaptive decision

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

Re-jagged AR4JA LDPC codes and their applications

This work investigated the performance of a newly developed protograph-based low-density parity-check code (LDPC) families belonging to accumulate-repeat-4-jagged-accumulate codes. The proposed code has hierarchical irregularity and quasi-cyclic property that retains it to be suitable for fast encoder and decoder implementation. The code used in this work is a rate-compatible linearly punctured code. The modified iterative decoding algorithm as mentioned in the literature is used along with a newly proposed encoder and simulation has been done for proposed LDPC coded orthogonal frequency division multiplexing (OFDM) link over wireless and optical wireless channels with hard- and soft-decision decoding. The code relates to new methods for designing rate-compatible families of protographs of different rates, all having the linear minimum distance property showing small performance degradation compared with the threshold. The parity-check matrix is composed of small identical modules to reduce the routing complexity of the decoder. The main essence of this code lies in the fact that LDPC codes of arbitrarily large size can be built by expanding from individual protographs or rate-compatible protograph families.

Structured quasi‐cyclic low‐density parity‐check codes based on cyclotomic cosets

This study considers the construction of four-cycle free quasi-cyclic low-density parity-check (QC-LDPC) codes. These codes are based on the cyclotomic cosets of q modulo n where q is a prime power, n is a prime and (n, q) = 1. If s is the order of q modulo n, then n − 1 = sl for some integer l. Then there are l distinct cyclotomic cosets Cai , 1 ≤ i ≤ l. Concatenation of the l circulant matrices formed using these sets gives an s × sl matrix M co(n, q). In addition, the Kronecker product of the transpose of ∪ i Cai with itself modulo n gives an sl × sl matrix M kr(n, q). Replacing the entries of these matrices with their associated dispersed binary n × n matrices provides binary QC-LDPC codes with girth at least six. Furthermore, for any prime power q′ such that q′ = n + 1 or q′ ≥ 2n, these two matrices can be used to construct q′-ary QC-LDPC codes with girth at least six. These constructions produce large classes of four-cycle free binary and non-binary QC-LDPC codes. Among the structured LDPC codes, the introduced technique, from code-construction-complexity perspective, which is an engineering factor, is at least among the best ones if not the best. Performance results are presented which show that the codes obtained perform well over additive white Gaussian noise channel with the iterative sum-product decoding algorithm.

Quantization Methods of the Reliability-Based Iterative Decoding Algorithm for LDPC Codes

This paper investigates the quantization methods of the reliability-based iterative decoding algorithm for LDPC codes. For the uniform quantization, we present a new design criterion to determine the quantization parameters with the clipping interval/probability. Compared to the original parameters setting, the presented design criterion can achieve higher resolution with the allowable quantization distortions. The presented parameter design criterion can be extended to the non-uniform quantization with a slight modification. Simulation results show that, the decoding algorithm can achieve better BER performances and faster convergence rate with smaller quantization bit when compared to the original parameters setting.

On the design of a low-complexity joint bit-packet coding scheme for AWGN channels

In this paper, a low-complexity joint design of bit-level and packet-level coding is investigated. In the proposed design structure, a low-complexity iterative decoding algorithm is considered, which is capable of using the Gaussian approximation method for analysing the decoding performance. When the performance of the bit-level coding is given, we analyse the asymptotic convergence of the packet-level coding, which is utilised for optimising the rate of the packet-level code. Based on our proposed optimisation method, an optimal code rate for the scheme can be theoretically acquired. Our numerical results show that the proposed low-complexity joint bit-packet coding scheme has an attractive performance.

A Multivariate Weight Enumerator for Tail-biting Trellis Pseudocodewords

Tail-biting-trellis representations of codes allow for iterative decoding algorithms, which are limited in effectiveness by the presence of pseudocodewords. We introduce a multivariate weight enumerator that keeps track of these pseudocodewords. This enumerator is invariant under many linear transformations, often enabling us to compute it exactly. The extended binary Golay code has a particularly nice tail-biting-trellis and a famous unsolved question is to determine its minimal AWGN pseudodistance. The new enumerator provides an inroad to this problem.

Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree

In this letter, a new reliability-based iterative majority-logic decoding (RBI-MLGD) algorithm that computes the extrinsic information of previous iterations of the variable node is proposed. This decoding algorithm is called historical-extrinsic reliability-based iterative decoder (HE-RBID) and improves the bit-error-rate performance of the previous RBI-MLGD. HE-RBID is particularly interesting for codes with a low degree of variable node, where traditional RBI-MLGD algorithms do not provide a good behavior. HE-RBID ensures a good performance without searching for the minimum at the check node and only by exchanging 1-bit messages between variable and check nodes.

Turbo codes for multi-hop wireless sensor networks with decode-and-forward mechanism

Wireless channels are prone to many impairments, such as noise and fading. Weak channels between the nodes in the wireless sensor network (WSN) can cause reception of erroneous packets. Retransmission mechanisms are mainly used to tackle the problem of erroneous reception in WSN communication protocols. Weak channels can cause high number of retransmissions in order to deliver a packet correctly, which will consume high energy of both the transmitting and the receiving nodes. Error correcting codes (ECCs) can be used to reduce number of retransmissions, but most ECCs have complex decoding algorithms, which leads to high processing energy consumption at the receiving nodes in the WSN. In this paper, we present a low power consumption decode-and-forward approach for the multi-hop WSNs; a serial concatenation convolutional codes (SCCC) encoder is implemented at the source node while the complex iterative decoding algorithm is shifted to the sink (base station). The intermediate nodes run a Viterbi decoding algorithm to decode only the inner code of the SCCC encoder. We investigate the effect of changing constraint length of both the inner and the outer codes and the effect of changing encoding block size. We show that most packets can be decoded at the base station at low signal-to-noise ratio (SNR) channels with the penalty of small energy loss in decoding the packet at the nodes in the network.

Soft decision iterative error and erasure decoder for Reed–Solomon codes

A list decoding algorithm for iterative soft-decision decoding of Reed–Solomon (RS) codes is proposed in this study. The algorithm erases a combination of least reliable symbols and iteratively flips a new combination of least reliable bits in the received sequence. The symbol error correction capability of the algebraic hard decision RS decoder is extended up to the minimum Hamming distance of the code. A gain in performance is exhibited either at a lower or similar iteration complexity as compared to other iterative soft decision decoders of similar type. A complexity comparison with some of the comparable soft decision decoders is given. Simulation results for different modulation schemes and channel types are presented in this study for a comparison with other soft decision decoders of a similar kind.

Recursive method for generating column weight 3 low‐density parity‐check codes based on three‐partite graphs

In this study, a method is presented to construct column weight 3 (CW3) low-density parity-check (LDPC) codes using three-partite graphs. Let Gb be a bipartite graph and Ng be the set of all minimum length cycles in Gb. Using Gb and Ng, a three-partite graph denoted G(Gb, Ng), or simply Gt, is formed. Let T be the set of length 3 cycles in Gt and Ta be the set of three element subsets of vertices in Gt such that each of these subsets form a subgraph with no edges in Gt and has precisely one element in each section of Gt. Furthermore, let H be the binary matrix in which the set of rows represent the set of vertices of Gt, the columns represent the elements of V:= T ∪ Ta, and hij = 1 if and only if the ith vertex of Gt belongs to the jth three element set in V. Then H is a CW3 binary matrix. Using the Tanner graph representing H, a recursive construction for CW3 LDPC codes is provided. Applying a simple restriction on T and Ta, codes free of length 4 cycles are generated. Euclidean and finite geometry codes are used as the base codes for generating new CW3 LDPC codes. Results are presented which show that these new codes perform well in an additive white Gaussian noise (AWGN) channel with the iterative sum-product decoding algorithm.

Performance Analysis and Implementation for Nonbinary Quasi-Cyclic LDPC Decoder Architecture

Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity iterative decoding algorithms have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high complexity and long latency. In this brief, highly efficient check node processing scheme, which the processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are proposed. Compare with previous works, less than 52% could be reduced for the latency of check node unit. In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NBQC-LDPC decoder.

Fast and Accurate Error Floor Estimation of Quantized Iterative Decoders for Variable-Regular LDPC Codes

In this letter, we propose a fast and accurate technique to estimate the error floor of variable-regular low-density parity-check (LDPC) codes under quantized iterative decoding algorithms. The technique, which is based on enumerating the dominant elementary trapping sets of the code, provides significant improvement over existing methods in terms of speed and accuracy.

Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes

This paper presents two iterative decoding algorithms for a class of non-binary two-step majority-logic (NB-TS-MLG) decodable cyclic codes. A partial parallel decoding scheme is also introduced to provide a balanced trade-off between decoding speed and storage requirements. Unlike non-binary one-step MLG decodable cyclic codes, the Tanner graphs of which are 4-cycle-free, NB-TS-MLG decodable cyclic codes contain a large number of short cycles of length 4, which tend to degrade decoding performance. The proposed algorithms utilize the orthogonal structure of the parity-check matrices of the codes to resolve the degrading effects of the short cycles of length 4. Simulation results demonstrate that the NB-TS-MLG decodable cyclic codes decoded with the proposed algorithms offer coding gains as much as 2.5 dB over Reed-Solomon codes of the same lengths and rates decoded with either hard-decision or algebraic soft decision decoding.

Finite Field Spreading for Multiple-Access Channel

As a generalization of the binary spreading scheme in conventional direct-sequence code-division multiple-access (DS-CDMA) and interleave-division multiple-access (IDMA), a finite field spreading scheme is proposed for a synchronous multiple-access channel (MAC) with Gaussian noise and equal-power users. For each user, each information symbol over a finite field is spread into a length-L field vector by L-field multiplications. At the receiver, an iterative multi-user decoding algorithm on a factor graph is developed to recover each user's information symbol. To estimate the bit error rate performance of an uncoded finite field spreading system, an extrinsic information transfer analysis of the finite field despreading is given. This analysis shows that in addition to overcoming multi-user interference, the finite field spreading scheme can also provide an additional coding gain to overcome Gaussian noise compared with the conventional spreading scheme. This coding gain increases with the field order. The finite field spreading serially concatenated with a nonbinary low-density parity-check (LDPC) code, with field order 64, approaches the MAC capacity within 0.26 dB at a sum rate of 0.25.