Iterative Bit Research Articles

A 1.2v ΔΣ ADC Modulator Using 4-bit SAR Quantizer for Biomedical Applications by using 65nm CMOS Technology

This research focuses on enhancing Sigma-Delta ADC modulators for biomedical applications by leveraging the working principle of Successive Approximation ADC circuits. The proposed modulator includes a comparator, DAC, successive approximation register, and control circuit. The operational process begins with the sample and holds circuit-initiating conversions by sampling the input signal, and then compared with the DAC output. Using a 4-bit example, the successive approximation register refines the DAC output through iterative bit adjustments until the closest digital code approximation to the input is voltage independent of input voltage, occurring incrementally one bit at a time. The proposed enhancement aims to optimize Sigma-Delta ADC modulator performance for biomedical applications, ensuring high resolution and speed. Typical conversion speeds range from 2 to 5 MSPS, with resolutions varying from 8 to 16 bits, contributing to improved precision and efficiency in capturing and digitizing biomedical signals.

Area-Efficient Realization of Binary Elliptic Curve Point Multiplication Processor for Cryptographic Applications

This paper proposes a novel hardware design for a compact crypto processor devoted to elliptic-curve point multiplication over GF(2233). We focus on minimizing hardware usage, which we obtain using an iterative bit–serial finite field modular multiplier for polynomial coefficient multiplication. The same multiplier is also used for modular squares and inversion computations, further optimizing the hardware footprint. Our design offers flexibility by permitting users to load different curve parameters and secret keys while keeping a low-area hardware design. To efficiently generate the control signals, we utilize a finite-state-machine-based controller. We have implemented the proposed crypto processor on Virtex-6 and Virtex-7 FPGA devices, and we have evaluated its performance at clock frequencies of 100, 50, and 10 MHz. Specifically, for one point multiplication computation on Virtex-7 FPGA, our crypto processor uses 391 slices, attains a maximum frequency of 161 MHz, has a latency of 4.45 ms, and consumes 77 mW of power. These results, along with a comparison to state-of-the-art designs, clearly demonstrate the practicality of our crypto processor for applications requiring efficient and compact cryptographic computations.

Nonlinear complication functions for symmetric stream ciphers

Currently, nonlinear Boolean functions are being investigated very actively around the world. However, many open questions remain in this area. The theory of nonlinear Boolean functions suitable for use in robust cryptographic algorithms is largely incomplete. Despite the presence of numerous publications on these topics, many issues related to the interrelation of design characteristics affecting the performance of the generator and its cryptographic characteristics are still open. The generation of a special type of sequences, called de Brain sequences, with minimal hardware and software costs, the rationale for their use as non-linear functions of the complexity of stream encryption systems, is the main theme of this work. The paper presents estimates of cryptographic indicators of nonlinear complexity functions of iterative bit sequence generators with various characteristics of the generated sequence, such as linear complexity and autocorrelation.

Terminated Staircase Codes for NAND Flash Memories

In this paper, we propose novel terminated staircase codes for NAND flash memories. Specifically, we design a rate 0.89 staircase code whose component code is a Bose–Chaudhuri–Hocquenghem (BCH) code, for flash memories with page size of 16K bytes. Different from most conventional unterminated staircase codes, we propose a novel coding structure by performing cyclic redundancy check (CRC) encoding and decoding on each component codeword including information bits and parity bits. The CRC bits are protected by both row and column codewords. Furthermore, a novel iterative bit flipping algorithm is developed to solve stall patterns and lower the error floor. Based on our design, we perform an improved analysis on the error floor. We prove and show that our proposed decoding algorithm can solve more stall patterns which leads to a lower error floor compared with conventional staircase codes. Numerical results show that our terminated staircase codes outperform the stand-alone BCH codes and the conventional staircase codes.

Improved iterative convergence method in Q-ary LDPC coded high order PR-CPM

The Q-ary low-density parity-check (LDPC) coded high order partial response continuous phase modulation (PR-CPM) with double iterative loops is investigated. This scheme shows significant improvements in power and bandwidth efficiency, but at the expense of long iterative decoding delay and computational complexity induced by the improper match between the demodulator and the decoder. To address this issue, the convergence behavior of Q-ary LDPC coded CPM is investigated for the Q=2 and Q>2 cases, and an optimized design method based on the extrinsic information transfer chart is proposed to improve the systematic iterative efficiency. Simulation results demonstrate that the proposed method can achieve a perfect tradeoff between iterative decoding delay and bit error rate performance to satisfy real-time applications.

Dynamic iteration stopping algorithm for non-binary LDPC-coded high-order PRCPM in the Rayleigh fading channel

This paper mainly studies the association between non-binary low-density parity-check codes and high-order partial response continuous phase modulation, which prevents information loss in the mutual conversion of bit and symbol probabilities. Although the iterative detection and decoding technique applied in this system can obtain good performance/complexity tradeoff, the iterative process still encounters the problems of positive feedback and relatively large decoding delay, similar to other iterative coded modulation systems. The inhibitory effects of different extrinsic information exchange methods on positive feedback under different signal-to-noise ratio (SNR) conditions are investigated in this work to address this issue. Two dynamic iterative stopping algorithms, namely, cross entropy and hard decision aided combined with weighted extrinsic information exchange for cases with medium and high SNRs, are then proposed. Extrinsic information exchange between the demodulator and the decoder is conducted in the two algorithms through weighted processing. Iterative detection is subsequently performed based on two stopping criteria of dynamic iterative decoding. Theoretic analysis and simulation results for the Rayleigh fading channel show that the combination of weighted extrinsic information exchange and the two dynamic iterative stopping algorithms effectively resists positive feedback and improves the convergence of iterative detection and bit error rate performance. Such a combination also reduces the average iteration number to improve the real-time performance of iterative detection and decoding.

Joint bit loading and power allocation for downlink minimum mean square error combining based multi‐carrier code division multiple access systems

The performance of a downlink multi-carrier code-division multiple-access (MC-CDMA) system heavily depends on the receiver type at the user side. The minimum mean square error-combining scheme possesses the finest performance. However, the resource allocation problem becomes a highly complex task because of multiple access interference. This study investigates a realistic scenario, where the base station determines the bit loading and power for all downlink users with both the power and bit error rate (BER) constraints to maximise the overall system throughput. The authors first derive the instantaneous signal to interference and noise ratio (SINR) and then approximate data transmission as an equivalent M-QAM system with a signal-to-noise ratio (SNR) equal to the instantaneous SINR of that user. Combined with accurate BER formulas of M-QAM system, the authors estimate the BER for each user given a set of power and bit loading configuration. Finally, the authors develop an iterative joint bit loading and power allocation algorithm to maximise the system throughput. The simulation results show that the proposed solution achieves performance close to the optimal one and maintains the BER close to the desired target.

Performance evaluation of time-multiplexed and data-dependent superimposed training based transmission with practical power amplifier model

The increase in the peak-to-average power ratio (PAPR) is a well known but not sufficiently addressed problem with data-dependent superimposed training (DDST) based approaches for channel estimation and synchronization in digital communication links. In this article, we concentrate on the PAPR analysis with DDST and on the spectral regrowth with a nonlinear amplifier. In addition, a novel Gaussian distribution model based on the multinomial distribution for the cyclic mean component is presented. We propose the use of a symbol level amplitude limiter in the transmitter together with a modified channel estimator and iterative data bit estimator in the receiver. We show that this setup efficiently reduces the regrowth with the DDST. In the end, spectral efficiency comparison between time domain multiplexed training and DDST with or without symbol level limiter is provided. The results indicate improved performance for DDST based approaches with relaxed transmitter power amplifier requirements.

Highly scalable JPEG image transmission with unequal error protection and optimal feedback

This paper investigates the performance of three different Unequal Error Protection (UEP) schemes for progressive JPEG image transmission using delay-constrained hybrid ARQ, with iterative bit and symbol combining. The first UEP scheme considers only the optimization of channel code-rates and keeps the number of retransmissions fixed for all the subbands of the image. The second one optimizes both the channel code-rates and retransmissions, while the third only considers the optimal allocation of retransmission requests. The UEP schemes are designed with two different coding techniques. The first one employs Rate Compatible Punctured Turbo Codes (RCPT) with iterative bit combining and, is suitable for applications requiring high power efficiency. For the second one we propose a new coding strategy, Rate Compatible Punctured Turbo Trellis Coded Modulation (RCPTTCM) with iterative symbol combining, which provides high scalability and bandwidth efficiency. Gains of over 9 dB in Peak-Signal-to-Noise-Ratio are obtained with the UEP schemes as compared to their corresponding Equal Error Protection (EEP) schemes.

Iterative bit and power allocation for multi-cell orthogonal frequency division multiplexing with minimum variance distortionless response beamforming

This paper develops bit and power allocation schemes with beamforming for multi-cell orthogonal frequency division multiplexing (OFDM) systems on uplink. The model of the multi-cell channel with frequency reuse is considered. The transmit signal from each mobile causes interference to the received signals of other base stations. The schemes aim to minimise the total mobile transmit power while satisfying the required data rate and the bit error rate (BER) of each mobile. The proposed schemes offer better performance than that of the fixed bit allocation method. The proposed distributed allocation scheme reduces computational complexity compared to the proposed centralised multi-user greedy method with insignificant performance degradation. The simulation results are presented to demonstrate the efficacy of the proposed schemes.

Performance of joint source–channel decoding with iterative bit combining and detection

A joint source–channel decoding scheme (JSCD) with iterative bit combining (IBC) is proposed, which exploits two types of a priori information. The first one is the a priori bit probabilities obtained from source statistics, and the second is the channel a priori probabilities obtained from saved extrinsic information of previous transmissions. The JSCD-IBC scheme also incorporates iterative detection as both a stopping criteria and mechanism for triggering retransmissions. This adds an implicit adaptivity to the system and prevents excess iterations/retransmissions from being effected. The performance of the JSCD-IBC scheme is evaluated with four different iterative detection schemes and also two different types of variable length codes, Huffman and reversible variable length codes. Simulation results show that a significant performance gain in terms of bit error rate, throughput, and number of iterations can be achieved with the JSCD-IBC scheme as compared to a separate decoding scheme.

On the Error Correction of Regular LDPC Codes Using the Flipping Algorithm

The iterative bit flipping algorithm is applied to the standard regular low-density parity-check (LDPC) code ensemble. In the past, it was shown, for a typical code in the ensemble with left degree at least five and block length sufficiently large, that this algorithm can correct a linear (in the block length) number of worst case errors. In this paper, this result is extended to the case where the left degree is at least four. For the case where the left degree is larger than four, an improvement, compared to existing results, of several orders of magnitude is obtained on the fraction of worst case errors that can be corrected. It is also shown how the results can be further improved when random errors produced by the channel (as opposed to worst case errors) are considered.

On Multi-User EXIT Chart Analysis Aided Turbo-Detected MBER Beamformer Designs

This paper studies the mutual information transfer characteristics of a novel iterative soft interference cancellation (SIC) aided beamforming receiver communicating over both additive white Gaussian noise (AWGN) and multipath slow fading channels. Based on the extrinsic information transfer (EXIT) chart technique, we investigate the convergence behavior of an iterative minimum bit error rate (MBER) multiuser detection (MUD) scheme as a function of both the system parameters and channel conditions in comparison to the SIC aided minimum mean square error (SIC-MMSE) MUD. Our simulation results show that the EXIT chart analysis is sufficiently accurate for the MBER MUD. Quantitatively, a two-antenna system was capable of supporting up to K=6 users at Eb/Na=3dB, even when their angular separation was relatively low, potentially below 20deg.

Iterative multiuser receivers for CDMA channels: an EM-based approach

Maximum-likelihood detection for the multiuser code-division multiple-access (CDMA) channel is prohibitively complex. This paper considers new iterative multiuser receivers based on the expectation-maximization (EM) algorithm and related, more powerful "space-alternating" algorithms. The latter algorithms include the SAGE algorithm and a new "missing parameter" space-alternating algorithm that alternately updates individual parameter components or treats them as probabilistic missing data. Application of these EM-based algorithms to the problem of discrete parameter estimation (i.e., data detection) in the Gaussian multiple-access channel leads to a variety of convergent receiver structures that incorporate soft-decision feedback for interference cancellation and/or sequential updating of iterative bit estimates. Convergence and performance analyses are based on well-known properties of the EM algorithm and on numerical simulation.

Space-frequency localized image compression

Subband and wavelet-based image compression can be viewed as frequency oriented techniques because each subimage in the decomposition is essentially a band-pass version of the original image. The authors suggest a space-frequency partition scheme to fully exploit the excellent localization properties of wavelets in both the spatial and frequency domains. Due to the relatively large number of blocks in this partition compared with traditional subband coders, the rate required for communicating the quantizer configurations must be taken into account. An iterative bit allocation algorithm is suggested that minimizes the mean square error given the overall rate for specifying the quantization configuration and for quantizing the wavelet coefficients. Images encoded using scalar quantization under this scheme show improvements in PSNR versus rate over traditional subband and wavelet-based methods.

A Simple Algorithm for Global Data Flow Analysis Problems

A simple, iterative bit propagation algorithm for solving global data flow analysis problems such as “available expressions” and “live variables” is presented and shown to be quite comparable in speed to the corresponding interval analysis algorithm. This comparison is facilitated by a result relating two parameters of a reducible flow graph (rfg). Namely, if G is an rfg, d is the largest number of back edges found in any cycle-free path in G, and k is the length of the interval derived sequence of G, then $k \geqq d$. (Intuitively, k is the maximum nesting depth of loops in a computer program, while d is a measure of the maximum loop-interconnectedness.) The node ordering employed by the simple algorithm is the reverse of the order in which a node is last visited while growing any depth-first spanning tree of the flow graph. In addition, a dominator algorithm for an rfg is presented which takes O(edges) bit vector steps.