Irregular Low-density Parity-check Research Articles

Optimal Design of a Gallager B Noisy Decoder for Irregular LDPC Codes

In this letter, we study the performance of a noisy Gallager B decoder used to decode irregular low-density parity-check (LDPC) codes. We derive the final bit error rate (BER) as a function of both the transmission noise and processing errors. We allow different components of the decoder associated with certain computational units (i.e., bit and check nodes of varying degrees) to have different processing errors. We formulate an optimization problem to distribute available processing resources across different components of a noisy decoder to achieve minimal BER. Simulations demonstrate that the optimal resource allocation derived from our analysis outperforms uninformed (random) resource assignment.

Performance analysis of protograph-based low-density parity-check codes with spatial diversity

In wireless communications, spatial diversity techniques, such as space-time block code and single-input multiple-output (SIMO), are employed to strengthen the robustness of the transmitted signal against channel fading. This article studies the performance of protograph-based low-density parity-check (LDPC) codes with receive antenna diversity. The authors first propose a modified version of the protograph extrinsic information transfer algorithm and use it for deriving the threshold of the protograph codes in a SIMO system. The authors then calculate the decoding threshold and simulate the bit-error rate (BER) of two protograph codes (accumulate-repeat-by-3-accumulate (AR3A) code and accumulate-repeat-by-4-jagged-accumulate (AR4JA) code), a regular (3,6) LDPC code and two optimised irregular LDPC codes. The results reveal that the irregular codes achieve the best error performance in the low signal-to-noise-ratio (SNR) region and the AR3A code outperforms all other codes in the high-SNR region. Utilising the theoretical analyses and the simulated results, the authors further discuss the effect of the diversity order on the performance of the protograph codes. Accordingly, the AR3A code stands out as a good candidate for wireless communication systems with multiple receive antennas.

Decoder-Optimised Progressive Edge Growth Algorithms for the Design of LDPC Codes with Low Error Floors

A novel construction for irregular low-density parity-check (LDPC) codes based on a modification of the Progressive Edge Growth (PEG) algorithm is presented. Edge placement of the PEG algorithm is enhanced by use of the Sum-Product algorithm in the design of the parity-check matrix. The proposed algorithm is highly flexible in block length and rate. The codes constructed by the proposed methods are tested in the AWGN channel and significant performance improvements are achieved. The flexibility of the proposed decoder optimisation operation is then shown by its use in modifying the Improved PEG (IPEG) algorithm to achieve further performance gains.

A Practical Joint Network-Channel Coding Scheme for Reliable Communication in Wireless Networks

In this paper, we propose a practical scheme, Non-Binary Joint Network-Channel Coding (NB-JNCC), for reliable multi-path multi-hop communication in arbitrary large-scale wireless networks. NB-JNCC seamlessly couples channel coding and network coding to effectively combat the detrimental effect of fading of wireless channels. Specifically, NB-JNCC combines non-binary irregular low-density parity-check (LDPC) channel coding and random linear network coding through iterative joint decoding, which helps to fully exploit the spatial diversity and redundancy residing in both channel codes and network codes. In addition, since it operates over a high order Galois field, NB-JNCC can be directly combined with high order modulation without the need of any bit-to-symbol conversion nor its inverse. Through both analysis and simulation, we demonstrate the significant performance improvement of NB-JNCC over other schemes.

Code-aided turbo synchronisation using irregular low-density parity check codes

An efficient scheme for iterative carrier recovery by using irregular low-density parity check (LDPC) codes is proposed at low signal-to-noise ratio (SNR) conditions. Owing to the significant effect of decoding extrinsic information on the carrier estimation algorithms, deficiency of extrinsic information from decoding caused by large residual frequency or phase offsets in initial iterations will result in incorrect parameter estimation and compensation, which would fail to converge toward low BER in decoding process. Irregular LDPC codes have inherence unequal error protection (UEP) capabilities wherein the high-degree nodes tend to correct their value more quickly than low-degree nodes. The more reliable information, which is provided by the high-degree nodes of irregular LDPC code in initial iterations, can be used to offer more reliable soft information for carrier synchronisation even in poor channel conditions, which leads to improvement of the carrier parameter estimation performance. The simulation results indicate that the more reliable information from irregular LDPC codes can cope with large frequency, phase uncertainty region and speed up the convergence properties for iterative synchronisers when comparing with regular LDPC codes with same parameters.

A Design of ALT LDPC Codes Using Circulant Permutation Matrices

In this paper, we propose a simple H parity check matrix from the CPM(circulant permutation matrix), which can easily avoid the cycle-4, and approach to flexible code rates and lengths. As a result, the operations of the submatrices will become the multiplications between several CPMs, the calculations of the LDPC(low density parity check) encoding could be simplest. Also we consider the fast encoding problem for LDPC codes. The proposed constructions could lead to fast encoding based on the simplest matrices operations for both regular and irregular LDPC codes.

Lowering Error Floors of Irregular LDPC Codes by Combining Construction and Decoding

Irregular low-density parity-check (LDPC) codes generally have good decoding performance in the waterfall region, but they exhibit higher error floors than regular ones. In this letter, we present a hybrid method, which combines code construction and the iterative decoding algorithm, to tackle this problem. Simulation results show that the proposed scheme decreases the error floor significantly for irregular LDPC codes over binary-input additive white Gaussian noise (BIAWGN) channel.

Generalised low-density parity-check codes with binary cyclic codes as component codes

Irregular low-density parity-check (LDPC) codes outperform turbo codes for the block length 10 4 and above. This study introduces generalised LDPC (GLDPC) codes with binary cyclic codes as component codes whose performance is better than that of irregular LDPC codes. The codes are found by optimising degree distributions. The authors also present some simulation results, which show that the codes surpass the irregular LDPC codes.

Bit-error rate analysis of low-density parity-check codes with generalised selection combining over a Rayleigh-fading channel using Gaussian approximation

Bit-error rate (BER) expressions of generalised selection combining with low-density parity-check (LDPC) codes, using binary phase-shift keying signals, over an independent and identically distributed Rayleigh-fading channel are derived using the Gaussian approximation (GA) approach. BER results for both selection combining and maximum-ratio combining can be computed from this BER expression as special cases. The symmetry and stability conditions of both density evolution (DE) and GA analysis are also studied. The degree distribution for irregular LDPC codes is optimised using differential evolution. The theoretical results are compared with both simulation results and DE thresholds. These BER expressions allow us to achieve a significant reduction in computational complexity for analysing the system performance as compared to simulation and DE.

Improved design of bit mapping based on EXIT-chart analysis for DVB-T2 system

In this paper, we focus on the design of bit mapping scheme to improve the error-control performance for the second generation digital video broadcasting-terrestrial (DVB-T2) standard. Generally in the case of low-density parity-check (LDPC)-coded modulation system, the nonuniform bit reliabilities inherent to the high-order modulation and irregular LDPC code imply the mismatch between the decoder and the demodulator. Hence, the bit mapping is plugged between the two modules to match the unequal error protections (UEPs) of different coded bits to different modulation levels. This scheme gives a remarkable performance improvement with no added complexity in the bit-interleaved coded modulation (BICM) system. By performing the curve-fitting on the extrinsic information transfer (EXIT) chart, we propose a DEMUX design methodology to improve the bit mapping scheme. Design examples are given for the DVB-T2 system under the AWGN channel as well as the Rayleigh channel. Simulation results indicate that the proposed DEMUX schemes can even surpass the performance of the DEMUX operation specified in the DVB-T2 standard.

Joint iterative decoding for pragmatic irregular LDPC-coded multi-relay cooperations

In this article, a new kind of pragmatic simple-encoding irregular systematic low-density parity-check (LDPC) code for multi-relay coded cooperation is designed, where the introduced joint iterative decoding is performed in the destination based on a proposed joint Tanner graph for all the constituent LDPC codes used by the source and relays in multi-relay cooperation. The theoretical analysis and numerical results show that the coded cooperations outperform the coded non-cooperation under the same code rate, and also achieve a good trade-off between the performance and the decoding complexity associated with the number of relays. This performance gain can be credited to the additional exchange of extrinsic information from the LDPC codes used by the source and the relays in both ideal and non-ideal cooperations.

Comments on "Theoretical Analysis of a MAP Based Blind Frame Synchronizer"

In this comment, we present a new estimation procedure for the blind frame synchronization error rate (FSER) based on analysis in . Simulations verify that the estimate is tight for low density parity check (LDPC) codes having large column weight. We show that regular LDPC codes have better synchronization performance than irregular LDPC codes having the same row weight distribution.

Secret-Sharing LDPC Codes for the BPSK-Constrained Gaussian Wiretap Channel

The problem of secret sharing over the Gaussian wiretap channel is considered. A source and a destination intend to share secret information over a Gaussian channel in the presence of a wiretapper who observes the transmission through another Gaussian channel. Two constraints are imposed on the source-to-destination channel; namely, the source can transmit only binary phase shift keyed (BPSK) symbols, and symbol-by-symbol hard-decision quantization is applied to the received symbols of the destination. An error-free public channel is also available for the source and destination to exchange messages in order to help the secret sharing process. The wiretapper can perfectly observe all messages in the public channel. It is shown that a secret sharing scheme that employs a random ensemble of regular low density parity check (LDPC) codes can achieve the key capacity of the BPSK-constrained Gaussian wiretap channel asymptotically with increasing block length. To accommodate practical constraints of finite block length and limited decoding complexity, fixed irregular LDPC codes are also designed to replace the regular LDPC code ensemble in the proposed secret sharing scheme.

Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding

This paper presents a low-energy asynchronous interleaver for clockless fully parallel low-density parity-check (LDPC) decoding. The proposed data-transmission circuit based on a half-duplex single-track protocol makes it possible to realize a wire-efficient asynchronous interleaver with small energy consumption. Moreover, a data-monitoring system adaptively shuts down the asynchronous data-transmission circuit if not necessary, which reduces the number of data transmissions and, hence, the energy consumed. The clockless decoder with the proposed asynchronous interleaver is evaluated using a (1056,528) irregular LDPC code under a 90-nm CMOS process. As a result, the energy dissipation per uncoded bit at Eb/No of 5 dB becomes 54 pJ/bit with an uncoded throughput of 45.5 Gbps under a postlayout simulation. This represents a 92% decrease in energy per bit and a 1143% in throughput increase with respect to our previous clockless LDPC decoder.

Performance evaluation of irregular low-density parity-check codes at high signal-to-noise ratio

Elementary trapping sets (ETSs) have been found to be the main cause of error floor in the decoding of low-density parity-check (LDPC) codes. Moreover, irregular LDPC codes that avoid harmful [w; u; e] ETSs have been constructed and have shown to possess superior error performance compared with other LDPC codes. In this paper, we attempt to evaluate irregular LDPC code performance under an additive white Gaussian noise channel within the high SNR region using the importance sampling (IS) approach in conjunction with the identification of [w; u; e] ETSs. For any given irregular LDPC code, we will first apply a three-step method that aims to search as many ETSs within the code as possible. Then, we will classify these ETSs into different groups based on their labels, i.e., [w; u; e]'s. Further, by dividing the error region into various sub-regions centered by ETSs, we apply the IS simulator to evaluate the error rate of each of the sub-regions. Based on the error rates of all the sub-regions, we can estimate the overall error rate of the LDPC code. Results have indicated that our proposed IS scheme can produce speed-up gains up to 3.9×109 times compared to Monte Carlo simulations.

Power-efficient Irregular Repeat-Accumulate Encoded BICM-ID for 16-ary Signal Constellations

The design of power-efficient forward error correction techniques over additive white Gaussian noise (AWGN) and frequency non-selective fading channels is considered in this work. The aim of this paper is to investigate the application of BICM with iterative demodulation and decoding (BICM-ID) system with irregular repeat-accumulate (IRA) codes to minimize the bit error rate (BER) and determine the most suitable constellation and mapping pairs for designing power-efficient BICM-ID systems over AWGN and Rayleigh fading channels using the concept of channel capacity limit. Simulation results have confirmed that a remarkable BER improvement can be achieved using the proposed design criterion. Based on the IRA-encoded BICM-ID technique considered, the BER improvement gained is exhibited either as an additional coding gain, error floor elimination, or both. The code components include the IRA codes, irregular low-density parity-check (ILDPC) codes and convolutional codes (CC). The modulation technique considered is the widely-used 16-ary constellations with various bit mappings .

A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes

A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, we use a block parallel decoding scheme by suitably mapping between required memory banks and processing units in order to increase the decoding throughput. The proposed architecture is realized for a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device. The design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz with a maximum of 8 iterations.

Design of Finite-Length Irregular Protograph Codes with Low Error Floors over the Binary-Input AWGN Channel Using Cyclic Liftings

We propose a technique to design finite-length irregular low-density parity-check (LDPC) codes over the binary-input additive white Gaussian noise (AWGN) channel with good performance in both the waterfall and the error floor region. The design process starts from a protograph which embodies a desirable degree distribution. This protograph is then lifted cyclically to a certain block length of interest. The lift is designed carefully to satisfy a certain approximate cycle extrinsic message degree (ACE) spectrum. The target ACE spectrum is one with extremal properties, implying a good error floor performance for the designed code. The proposed construction results in quasi-cyclic codes which are attractive in practice due to simple encoder and decoder implementation. Simulation results are provided to demonstrate the effectiveness of the proposed construction in comparison with similar existing constructions.

Efficient construction of irregular codes with midterm block length and near-Shannon performance

In this study, the authors propose a new method for constructing irregular low-density parity-check codes (LDPC codes) with midterm or short block lengths. It is a Monte-Carlo simulation-based optimisation procedure called downhill simplex which uses progressive edge growth method for Tanner graph construction in cost function evaluations. It outperforms the density evolution (DE) method in both efficiency and performance. The efficiency of the authors' proposal mostly depends on the Monte-Carlo simulation time which owing to the midterm block lengths is relatively small compared to the time delay of the conventional DE method. Simulation results show that for block length of 3200 and a relatively low code rate 3/8, LDPC codes constructed using the authors' proposal noticeably outperform those constructed with DE method by more than 0.2 dB in the entire signal to noise ratio (SNR) range under AWGN channel.

Analysis of Stopping Constellation Distribution for Irregular Non-binary LDPC Code Ensemble

The fixed points of the belief propagation decoder for non-binary low-density parity-check (LDPC) codes are referred to as stopping constellations. In this paper, we give the stopping constellation distributions for the irregular non-binary LDPC code ensembles defined over the general linear group. Moreover, we derive the exponential growth rate of the average number of the stopping constellation distributions in the limit of large code length.