Irregular LDPC Research Articles

Multiple Scaling Extrinsic Soft Information for Improved Min-Sum Iterative Decoding of LDPC Codes

This paper presents an improved min-sum iterative decoding scheme for regular and irregular LDPC codes. The proposed decoding scheme scales the extrinsic soft information from variable nodes to check. Different scaling factors are applied for iterations and the scaling factors are obtained by a simplified vector optimization method.

Detailed Evolution of Degree Distributions in Residual Graphs with Joint Degree Distributions

Luby et al. derived evolution of degree distributions in residual graphs for irregular LDPC code ensembles. Evolution of degree distributions in residual graphs is important characteristic which is used for finite-length analysis of the expected block and bit error probability over the binary erasure channel. In this paper, we derive detailed evolution of degree distributions in residual graphs for irregular LDPC code ensembles with joint degree distributions.

Mapping for Iterative MMSE-SIC with Belief Propagation

Multiple-Input Multiple-Output (MIMO) wireless systems offer both high data rates and high capacity. Since different signals are transmitted by different antennas simultaneously, interference occurs between the transmitted signals. Each receive antenna receives all the signals transmitted by each transmit antenna simultaneously. The receiver has to detect each signal from the multiplexed signal. A Minimum Mean Square Error (MMSE) algorithm is used for spatial filtering. MMSE filtering can realize low complexity signal detection, but the signal output by MMSE filtering suffers from interference by the other signals. MMSE-SIC combines MMSE filtering and Soft Interference Cancellation (SIC) with soft replicas and can achieve good Bit Error Rate (BER) performance. If an irregular LDPC code or a turbo code is used, the reliability and BER of the information bits output by the decoder are likely to be higher and better than the parity bits. In MMSE-SIC, bits with poor reliability lower the accuracy of soft replica estimation. When the soft replica is inaccurate, the gain obtained by SIC is small. M-ary Phase Shift Keying (PSK) and M-ary Quadrature Amplitude Modulation (QAM) also achieve high data rates. Larger constellations such as 8PSK and 16QAM transfer more bits per symbol, and the number of bits per symbol impacts the accuracy of SIC. Unfortunately, increasing the number of bits per symbol is likely to lower the accuracy of soft replica estimation. In this paper, we evaluate three mapping schemes for MMSE-SIC with an LDPC code and a turbo code with the goal of effectively increasing the SIC gain. The first scheme is information reliable mapping. In this scheme, information bits are assigned to strongly protected bits. In the second scheme, parity reliable mapping, parity bits are assigned to strongly protected bits. The last one is random mapping. Computer simulations show that in MMSE-SIC with an irregular LDPC code and a turbo code, information reliable mapping offers the highest SIC gain. We also show that in MMSE-SIC with the regular LDPC code, the gains offered by the mapping schemes are very small.

Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms

In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy, according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under good channel condition. The synthesis result in 0.18 μm CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.1 1n) protocol achieves 810 [Mbps] throughput with 283 [mW] power consumption.

Lowering the Error Floors of Irregular LDPC Code on Fast Fading Environment with Perfect and Imperfect CSIs

Irregular LDPC codes can achieve better error rate performance than regular LDPC codes. However, irregular LDPC codes have higher error floors than regular LDPC codes. The Ordered Statistic Decoding (OSD) algorithm achieves approximate Maximum Likelihood (ML) decoding. ML decoding is effective to lower error floors. However, the OSD estimates satisfy the parity check equation of the LDPC code even the estimates are wrong. Hybrid decoder combining LLR-BP decoding algorithm and the OSD algorithm cannot also lower error floors, because wrong estimates also satisfy the LDPC parity check equation. We proposed the concatenated code constructed with an inner irregular LDPC code and an outer Cyclic Redundancy Check (CRC). Owing to CRC, we can detect wrong codewords from OSD estimates. Our CRC-LDPC code with hybrid decoder can lower error floors in an AWGN channel. In wireless communications, we cannot neglect the effects of the channel. The OSD algorithm needs the ordering of each bit based on the reliability. The Channel State Information (CSI) is used for deciding reliability of each bit. In this paper, we evaluate the Block Error Rate (BLER) of the CRC-LDPC code with hybrid decoder in a fast fading channel with perfect and imperfect CSIs where 'imperfect CSI' means that the distribution of channel and those statistical average of the fading amplitudes are known at the receiver. By computer simulation, we show that the CRC-LDPC code with hybrid decoder can lower error floors than the conventional LDPC code with hybrid decoder in the fast fading channel with perfect and imperfect CSIs. We also show that combining error detection with the OSD algorithm is effective not only for lowering the error floor but also for reducing computational complexity of the OSD algorithm.

Layered Wyner Ziv Video Coding

Following recent theoretical works on successive Wyner-Ziv coding (WZC), we propose a practical layered Wyner-Ziv video coder using the DCT, nested scalar quantization, and irregular LDPC code based Slepian-Wolf coding (or lossless source coding with side information at the decoder). Our main novelty is to use the base layer of a standard scalable video coder (e.g., MPEG-4/H.26L FGS or H.263+) as the decoder side information and perform layered WZC for quality enhancement. Similar to FGS coding, there is no performance difference between layered and monolithic WZC when the enhancement bitstream is generated in our proposed coder. Using an H.26L coded version as the base layer, experiments indicate that WZC gives slightly worse performance than FGS coding when the channel (for both the base and enhancement layers) is noiseless. However, when the channel is noisy, extensive simulations of video transmission over wireless networks conforming to the CDMA2000 1X standard show that H.26L base layer coding plus Wyner-Ziv enhancement layer coding are more robust against channel errors than H.26L FGS coding. These results demonstrate that layered Wyner-Ziv video coding is a promising new technique for video streaming over wireless networks.

Average Coset Weight Distribution of Multi-Edge Type LDPC Code Ensembles

Multi-Edge type Low-Density Parity-Check codes (MET-LDPC codes) introduced by Richardson and Urbanke are generalized LDPC codes which can be seen as LDPC codes obtained by concatenating several standard (ir)regular LDPC codes. We prove in this paper that MET-LDPC code ensembles possess a certain symmetry with respect to their Average Coset Weight Distributions (ACWD). Using this symmetry, we drive ACWD of MET-LDPC code ensembles from ACWD of their constituent ensembles.

A class of irregular ldpc codes with low error floor and low encoding complexity

In this letter, we propose a class of irregular structured low-density parity-check (LDPC) codes with low error floor and low encoding complexity by designing the parity check matrix in a triangular plus dual-diagonal form. The proposed irregular codes clearly lower the error floor and dramatically improve the performance in the waterfall region of error-rate curves. Being characterized by linear encoding complexity, the encoders of the proposed codes attain throughputs over 10 Gbit/s.

Irregular LDPC codes as concatenation of regular LDPC codes

In this letter, the construction of irregular LDPC codes obtained by concatenating regular ones is considered. These codes are analyzed for the binary symmetric channel (BSC). It is shown via proper distribution evolution that such concatenated codes have in general a threshold value weaker (but not necessarily much different) than their unconstrained counterparts for the BSC. On the other hand, they can offer advantages in term of convergence and error performance for lengths of practical interest and long enough to validate the degree distribution selection.

Generalization of Tanner's minimum distance bounds for LDPC codes

Tanner derived minimum distance bounds of regular codes in terms of the eigenvalues of the adjacency matrix by using some graphical analysis on the associated graph of the code. In this letter, we generalize Tanner's results by deriving a bit-oriented bound and a parity-oriented bound on the minimum distances of both regular and block-wise irregular LDPC codes.

Design of Efficiently Encodable Moderate-Length High-Rate Irregular LDPC Codes

Design of Efficiently Encodable Moderate-Length High-Rate Irregular LDPC Codes