IP Core Research Articles

Design and Application of Real‐Time and High‐Precision Seismic Acquisition Station in Antarctic Region

ABSTRACTIn this study, a polar seismic acquisition station based on the FPGA + ARM architecture was successfully developed. This system can achieve real‐time multifunctional acquisition and transmission of seismic signals and environmental information in the extreme low‐temperature environment of Antarctica at −40°C. The system adopts a modular design, with high‐precision data acquisition encoded by the main controller and uploaded to the host computer in real‐time. Integrated display controls enable real‐time data display and acquisition station location mapping for user interaction. We propose improving data transmission in traditional seismic acquisition stations by adopting a distributed computing model with data segment return. Integrating the first arrival picking algorithm as an IP core will reduce computational demands on the data processing center. This acquisition system features high precision (24‐bit), a wide dynamic range (> 130dB), low noise (0.5 V rms@40dB), and high‐precision timing control (200 ns). It supports real‐time wireless data transmission over 120 channels up to 1 km. The system also implements a self‐storage plus wired and wireless networking solution, allowing flexible networking based on actual needs. Test results indicate that the ice sheet thickness at the acquisition site is approximately 526.49 m, validating the experimental design's effectiveness and providing technical support for subsequent drilling and seismic exploration.

Ultra High multi channel clock frequency(THz, PHz, EHz, ZHz,YHz,XHz,WHz) baud rate speed PRBS Transceiver HDL RTL ASIC Design for Ultra High long Distance Wireless Communication Engineering Smart Computing Products/ Applications

The Key Objective is HDL RTL Design Architecture of Ultra high multi Clock Frequency Speed Rate ( MHz, GHz, THz, PHz, EHz, ZHz, etc) Bits Per Second Baud Rate ) P.R.B.S(Pseudo Random Binary Sequence) Transceiver Soft A.S.I.C IP Core product for identification of the property of Different Pseudo Random Binary Sequence Patterns (Seed Words) of 2e 7 -1, 2e10 -1, 2e 15 -1, 2e 23 -1, 2e 31 -1 tapped elements as per C.C.I.T.T-I.T.U Standards and IEEE-754 Single and Double Data Rate Data Precision Standards (32 bit & 64 Bit Data Width ) suited for Very Advanced Futuristic Hi-tech Smart High Speed Long Distance Wireless Digital Communication A.S.I.C Products / Applications like Space/Satellite, Aerospace and Large Data Processing and computing like High Speed Internet and Cloud Computing based Hi-Fi Industrial Data Automation Standard Ultra High Speed Wireless Communication A.S.I.C products and Applications-3G,4G,5G etc. The Multi channel PRBS Transceiver consists Transmitter and receiver of different PRBS patterns- 2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 NRZ. The data input transmitted and received serially in the form bit by bit. These different pattern sequences are Designated as per CCITT ITU 0.151/O.152/O.153 & AT&T Standards. The Aim and purpose of invention of Ultra high multichannel Clock frequency PRBS Transceiver is for transmit and receive data serially by using Tx_in and Tx_out, rxin, rxout signals and The Transceiver is processed the low frequency signal input with different high speed carrier wave frequencies in the form of different PRBS pseudo random binary sequence seed word bit/byte patterns -2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 NRZ and also on receiver side processed with the above patterns. Materials and Methods: Transmission and reception of Data serially based on the Deterministic random seed word pattern methods of different PRBS 2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 tapped sequence Elements and All these PRBS are purely synchronized with Ultra high clock frequency(MHz, GHz, THz, PHz, EHz, ZHz, YHz, XHz, WHz). The Soft IP Core Designed by System Verilog HDL/ Verilog HDL. RTL Design Simulation done by Synopsys VCS 2020.1 software and Altera Model-Sim Software and Logic Design Flow & Synthesis done by Xilinx ISE and Altera Quartus EDA Tools. Results: Generation of Simulation Display and waveform for Ultra High Clock frequency(MHz, GHz, THz, PHz, EHz, ZHz, YHz, XHz, WHz) Synchronized Pseudo Random Binary Sequence (PRBS) Register Transfer Level (RTL) Generators, Transceiver for efficient and effective High Quality Data transmission and Reception of Various tapped sequence patterns for Identification of property of different PRBS patterns2e7 -1, 2e10-1, 2e15-1, 2e23 -1, 2 31 -1 NRZ of Ultra high speed Long distance wireless engineering Applications/ products.

Design and Implementation of SoC-based Image Codec IP Cores

Design and Implementation of SoC-based Image Codec IP Cores

3D network-on-chip data acquisition system mapping based on reinforcement learning and improved attention mechanism

The three-dimensional Network-on-Chip (NoC) data acquisition system is designed to create a time-interleaved data acquisition system using NoC technology. In the design of NoC application systems, optimizing the mapping algorithm can effectively reduce network communication latency. Aiming at the mapping challenge of a large number of functional IP nodes in 3D NoC data acquisition system, the reinforcement learning and improved attention mechanism mapping algorithm (RA-Map) is proposed. The RA-Map mapping algorithm employs node function encoding and node position encoding to express the properties of an IP node in the task graph preprocessing. The local attention mechanism is used in the mapping network encoder, and the fusion of dynamic key node information is proposed in the decoder. The mapping result evaluation network achieves unsupervised training of the mapping network. These targeted improvements improve the quality of the mapping. Experimental results show that the RA-Map mapping algorithm can effectively model the IP core mapping. Compared with the DPSO algorithm and SA algorithm, the average communication cost of RA-Map mapping algorithm is reduced by 6.5 % and 8.5 %, respectively.

Design of Area Efficient Network-On-Chip Router: A Comprehensive Review

The number of uses for cutting-edge technologies has led to a further growth in a single chip's computational capacity. In this case, several applications want to build on a single chip for computing resources. As a result, connecting the IP cores becomes yet another difficult chore. The many-core System-On-Chips (SoCs) are being replaced by Network-On-Chip (NoC) as an on-chip connectivity option. As a result, the Network on Chip was created as a cutting-edge framework for those networks inside the System on Chip. Modern multiprocessor architectures would benefit more from a NoC architecture as its communication backbone. The most important components of any network structure are its topologies, routing algorithms, and router architectures. NoCs use the routers on each node to route traffic. Circuit complexity, high critical path latency, resource usage, timing, and power efficiency are the primary shortcomings of conventional NoC router architecture. It has been difficult to build a high-performance, low-latency NoC with little area overhead. This paper surveys previous methods and strategies for NoC router topologies and study of general router architecture and its components. Analysis is carried out to understand and work for a low latency, low power consumption, and high performance NoC router design that can be employed with a wide range of FPGA families. In the current work, we are structuring a modified four port router with the goals of low area and high performance operation.

A floating‐point multiplier based on angle representation method

SummaryThis article proposes a novel angle representation method for floating‐point number, which eliminates the need for DSP (Digital Signal Processor) resources and reduces the resource usage when performing floating‐point multiplication. Compared with the implementation of floating‐point multiplier using IP cores, the implementation of approximate multiplication based on lookup tables can achieve an average reduction of 58.2% in LUTs (look‐up tables) and an average increase of 20.4% in frequency for mantissa widths ranging from 3 to 12 bits. Additionally, it can also save an average of 23.2% in registers. Analysis of PDP (power‐delay product)/LUT to MRED (mean relative error distance)/PRED (probability of relative error distance) among other approximate multipliers shows that the proposed design extends the Pareto front. At last, simulation of a three‐level inverter is implemented to verify the effectiveness of the multiplier.

Securing Reusable IP Cores Using Voice Biometric Based Watermark

Securing Reusable IP Cores Using Voice Biometric Based Watermark

Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection

Long-term and effective detection of epileptic seizures is a crucial aspect of epilepsy monitoring and treatment. Addressing the resource overhead issue of wearable epilepsy detection devices, this paper proposes a lightweight hardware implementation scheme for epilepsy detection based on a reusable architecture empirical mode decomposition (EMD) and K-Nearest Neighbors (KNN). Firstly, EMD is used to extract epileptic features from electroencephalogram (EEG), optimized through a reusable architecture design and sawtooth transform to reduce hardware resource usage. Subsequently, a KNN classifier with similarity judgment mechanism is designed to improve the recognition efficiency. Implemented on TSMC 65 nm process, the circuit area is 1.91 mm2, operates at 1 V and 20 MHz, with a power consumption of 4.034 mW. Evaluation on the Bonn EEG dataset yielded a classification accuracy of 96 %, sensitivity of 98 %, and a single detection delay of 1.51 ms. The hardware design offers a simple structure, high accuracy, and low resource consumption, making it suitable for wearable epilepsy detection devices.

FPGA-Based Acceleration of Polar-Format Algorithm for Video Synthetic-Aperture Radar Imaging

This paper presents a polar-format algorithm (PFA)-based synthetic-aperture radar (SAR) processor that can be mounted on a small drone to support video SAR (ViSAR) imaging. For drone mounting, it requires miniaturization, low power consumption, and high-speed performance. Therefore, to meet these requirements, the processor design was based on a field-programmable gate array (FPGA), and the implementation results are presented. The proposed PFA-based SAR processor consists of both an interpolation unit and a fast Fourier transform (FFT) unit. The interpolation unit uses linear interpolation for high speed while occupying a small space. In addition, the memory transfer is minimized through optimized operations using SAR system parameters. The FFT unit uses a base-4 systolic array architecture, chosen from among various fast parallel structures, to maximize the processing speed. Each unit is designed as a reusable block (IP core) to support reconfigurability and is interconnected using the advanced extensible interface (AXI) bus. The proposed PFA-based SAR processor was designed using Verilog-HDL and implemented on a Xilinx UltraScale+ MPSoC FPGA platform. It generates an image 2048 × 2048 pixels in size within 0.766 s, which is 44.862 times faster than that achieved by the ARM Cortex-A53 microprocessor. The speed-to-area ratio normalized by the number of resources shows that it achieves a higher speed at lower power consumption than previous studies.

Comparative study: AutoDPR-SEM for enhancing CNN reliability in SRAM-based FPGAs through autonomous reconfiguration

Convolutional neural networks (CNNs) are widely adopted in safety-critical systems, including space applications and autonomous vehicles. Field-programmable gate arrays (FPGAs) based on SRAM are preferred for accelerating CNN computations due to their unique characteristics. However, the configuration memory of FPGAs is susceptible to single event effects (SEEs), which can corrupt computations and lead to misclassification of CNN outputs. In this study, we investigated the impact of SEEs on SRAM-based FPGAs with Two-Photon Absorption (TPA) laser fault injections through a comparative analysis of two popular CNN acceleration architectures: streaming architecture (SA) and single compute engine (SCE). Experimental results show that SA-based CNNs require more hardware resources but exhibit superior resilience against single event upsets (SEUs). Without any Radiation Hardened by Design (RHBD) protection, SCE has an error rate approximately twice as high as SA. To mitigate errors, the Xilinx IP core - Soft Error Mitigation (SEM) is used for error detection and correction, leading to error rate reductions of up to 50 % in both architectures. Importantly, we propose the AutoDPR-SEM (Autonomous Dynamic Partial Reconfiguration for Soft Error Mitigation) approach, which automatically reconfigures the SEM IP core when it remains idle due to uncorrectable errors. AutoDPR-SEM significantly improves CNN error rates, reducing errors by approximately 17.8 times in SCE and 14.8 times in SA. We also applied software level simulation to validate the TPA experiment, showing similar trends of the testing results across all models. In conclusion, the study confirms the feasibility of AutoDPR-SEM in both architectures, showcasing its potential to improve CNN error rates in safety-critical systems.

Peppa Pig: Experience Evolution and User Migration in Multi-industry Creative Consumption

The core IP image of the British animated film Peppa Pig, "Peppa", has seen an all-media explosion and multi-industry IP consumption since 2018, while transforming from a "child Peppa" to a "social person" symbol, becoming a youth subculture phenomenon worthy of attention. By combing through the rewriting or hype of Peppa as a cultural symbol in various media communication, we analyze the experience flow of cultural symbols behind Peppa culture in the communication process, as well as the phenomenon of user migration in multiple industries, and reflect on the creative consumption under the development trend of "new culture and creativity". Using Peppa Pig as a typical case of digital creativity, we propose the logic of user experience construction under two perspectives: product business line and user emotional engagement line. The cultural interpretation of Peppa by different user groups in different industries also inevitably leads to the alienation of Peppa, and Peppa with many different roles is typical. This also demonstrates the trend and crisis of creative IP in the development process: the synergistic evolution of digital creativity in multiple industries and the over-emphasis on experience consumption after the combination of the experience economy and the characteristics of the digital age may lead to creative misconception.

Elastic Gateway SoC design: A HW-centric architecture for inline In-Vehicle Network processing

The concepts of future mobility such as autonomous, connected, electric and shared vehicles are bringing a huge revolution to the automotive sector. We are seeing technologies typical from data centers fully embedded into vehicles, shifting from a mechanical-centric product, to an electronics-centric one. All the sensors and actuators embedded in vehicles need to exchange data in real time, in a safe and reliable way. As a result, the field of in-vehicle network (IVN) processing is currently an active research area. In previous work, we derived the requirements of future vehicle network processors and analyzed the state of the art of network processing platforms. From our study we concluded that there is currently no solution available capable of fulfilling all the requirements with the right level of performance. Now, in this work, we evaluate the novel Elastic Gateway (eGW) architecture which aims at fulfilling this gap, advancing towards future Gateway System/Network on Chip (SoC/NoC) solutions. Elastic Gateway SoC concept aims at synthesizing a scalable and future proof architecture embracing all new and already established functions and features demanded in a zonal gateway controller for the new era of mobility. It is composed of a set of configurable IP cores that allow for a full HW-based datapath implementation targeting good enough Quality of Service (QoS) and the minimum possible latency. We provide details of the internal architecture and how the different technologies required in future IVNs are integrated in eGW. With this, we are able to show how eGW meets the requirements of future network processing devices, enabling thus the current revolution.

Abeto: An automated benchmarking tool to manage heterogeneous IP core databases

System-level design makes use of building blocks, known as soft IP cores, to build complex developments. The usage of these IP cores allows to reduce design and verification time, and also to save costs. However, the use of third-party IP cores tends to present difficulties because of a lack of standardization in their organization, distribution and management, which derive in heterogeneous databases. Most of the time, system developers need to describe some additional code to enable the integration, verification and validation of the IP core, which is not available as part of their distribution. This implies acquiring a deep knowledge of each IP core, often with a large learning curve.In this work Abeto is presented, a new software tool for IP core databases management. It allows to easily integrate and use a heterogeneous group of IP cores, described in VHDL, with a unified set of instructions or commands. In order to do so, Abeto requires from every IP core some side information about its packaging and how to operate with the IP. Currently, Abeto provides support for a set of well-known EDA tools and has been successfully applied to the European Space Agency portfolio of IP cores for benchmarking purposes. To demonstrate its performance, mapping results for these IP cores on the novel NanoXplore BRAVE FPGA family are provided.

An Analysis of the Optus National Outage and Recommendations for Enhanced Regulation

On Wednesday, 8 November 2023 at about 4am, approximately 10 million Optus retail and 400,000 business customers lost network access as a result of the IP Core network shutdown. Optus stated that the cause of the network outage was a routine software upgrade that led to routing information updates from an international peering network causing key routers to disconnect from the network. This paper provides an analysis of the national outage, what information is needed to fully understand what occurred, and considers the lessons that might be learned.

A novel approach to generate trigonometric functions using high performance FPGA

This paper describes the novel approach to generate the trigonometric function sine wave with different amplitudes and different frequencies. The proposed design is synthesized using Xilinx ISE 14.7 using Verilog HDL programming language and simulated using the modelsim simulator. The sine wave generation is targeted on the high performance Zynq 7-series Zedoard FPGA (7020) which has a capability of programming language (PL) and processing system (PS). Generation of sine wave is carried out using Xilinx IP Core (DDS) approach with simulation, and synthesis. Zed board works on 28nm technology. Hardware device utilization summary of the design is analyzed along with the timing values. The power report of the design is extracted using the X power analyzer. Power analysis is compared with Micro wind software and X-power analyzer.

Development of a multifunctional real-time data processing system for interferometers on EAST

In the latest campaign of EAST experiments, two new interferometers were installed, a dispersion interferometer (DI) based on a Carbon Dioxide laser and a solid source interferometer (SSI) based on microwave multiplier sources. To make them available for the Plasma Control System (PCS) system, each of them needs to be provided with a real-time processing system to extract the detector output signal and afterward obtain the electron density information through signal processing. To obtain interferometer data quickly and reliably, a unified hardware template was applied to both interferometers. Three main parts are included in this hardware template — digitization, digital signal processing, and output modules. In particular, the digitization section uses a multi-channel Analog-to-Digital Convertor (ADC) to acquire the signals that need to be calculated. The digital signal processing part is implemented by an FPGA, which is the hardware basis of this multifunctional template that can be used for multiple interferometers. This section includes two main parts, wrapped density signal extraction and signal unwrapping. For DI it is a phase calculation based on the intensity ratio, while for SSI it is a phase calculation by means of FFT or phase demodulation. Both computational approaches form independent IP cores to build systems quickly, while these IP cores provide parameter interfaces to adapt to different application scenarios. The output module provides a variety of data transmission methods, including fiber optic transmission and Digital-Analog-Convertor (DAC) based analog transmission, to interface with PCS or other subsequent systems.This data processing system template has been applied to each of the above two interferometers and valid data were obtained in a recent EAST experiment campaign. It demonstrates the usefulness of the template and provides a reference for the design of data processing systems on future devices.

Research of the system-on-chip-based relay protection technology

The relay protection device is the core equipment that ensures the safe and stable operation of a power grid. With the open access of a large number of distributed generation, DC transmission and electric vehicles, a new deep low-carbon power system dominated by power electronic devices has gradually been formed. It is difficult for the traditional control and protection architecture, methods, and technology to meet the business characteristics and functional requirements of a diversified interaction, agile response, safety, and credibility of the power grid in the future. This paper presents a chip-based relay protection technology based on system-on-chip (SoC), which is described from four aspects, namely, the architectural design of the relay protection SoC, software and hardware cooperative relay protection based on the SoC IP core, experimental verification, and engineering application. The results show that the relay protection SoC proposed in this paper has significantly improved the performance of high-speed data acquisition and interaction through hardware algorithm engine acceleration and software and hardware collaborative computing, which is helpful to realize the local equipment operation and the integration of primary and secondary equipment, shorten the protection action time, and improve the speed, reliability, and stability of relay protection devices.

Design of CapEx and OpEx aware IP-over-WDM network using different types of traffic bypass and grooming techniques

To improve efficiency in setting up and operation of IP-over-WDM (IPoWDM) network, the network can be designed by minimizing either the capital expenditure (CapEx) or the operational expenditure (OpEx) in the planning phase. However, the CapEx-aware designed network may differ from the OpEx-aware designed network. Thus, Capex and OpEx need to be considered together to develop an expenditure-efficient network for a given planning period. Lightpath bypass and traffic grooming techniques help to minimize the required line card number in the core IP router. We design an expenditure (i.e., CapEx and OpEx put together for a given planning period) efficient IPoWDM network. We also review the effect of lightpath bypass and traffic grooming in the design. To design IPoWDM networks, we develop an optimization model and auxiliary-matrix-based heuristics to reduce the network’s total expenditure. The proposed methods judiciously deploy the network equipment at different places to reduce the total expenses and provide solutions for traffic grooming and placement of regenerators. We assume a realistic network framework where the bidirectional WDM equipment has finite transparent reach limit. The performance analysis shows that the multi-hop bypass approach provides more expenditure-efficient networks compared with the direct bypass and the non-bypass methods.

White Rabbit Expansion Board: Design, Architecture, and Signal Integrity Simulations

The White Rabbit protocol allows synchronization and communication via an optical link in an integrated, modular, and scalable manner. It provides a solution to those applications that have very demanding requirements in terms of synchronization. Field-programmable gate arrays are used to implement the protocol; additionally, special hardware is needed to provide the necessary clock signals used by the dual-mixer time difference for precise phase measurement. In the present work, an expansion board that allows for White Rabbit functionality is presented. The expansion board contains the oscillators required by the White Rabbit protocol, one running at 125 MHz and another at 124.922 MHZ. The architecture of this board includes two oscillator systems for tests and comparison. One is based on VCOs and another on crystal oscillators running at the desired frequencies. In addition, it incorporates a temperature sensor, from where the medium access control address is extracted, an electrically erasable programmable read-only memory, a pulse-per-second output, and a USB UART to access the White Rabbit IP core at the field-programmable gate array. Finally, to ensure the quality of the layout design and guarantee the level of synchronization desired, the results of the power and signal integrity simulations are also presented.

Acceleration and implementation of convolutional neural networks based on FPGA

Target detection algorithms are an important technology in the field of computer vision and usually need to be implemented on devices such as CPU or GPU with high computational power. However, traditional CPU are unable to support real-time processing and computations; the power consumption of GPU is relatively high and the application scenarios are limited. FPGA, with their high throughput rate, high power efficiency and reconfigurability, are the best platform for research on hardware acceleration of target detection algorithms. Therefore, how to implement efficient target detection algorithms on embedded devices is an important challenge. A method for YOLOv4-Tiny object detection algorithm accelerator based on FPGA is proposed and demonstrated in this paper. In this design, an optimization strategy is proposed, including the design of IP cores for convolutional computation in HLS, the fusion of batch normalization layers with convolutional layers, dynamic fixed-point 16-bit quantization, loop unrolling double-buffered storage and channel parallel acceleration, which can improve the computational performance and efficiency of the target detection algorithm. The YOLOv4-Tiny target detection algorithm was deployed on an FPGA development board, and experimental results showed that it achieved a computational performance of 18.32 GOP/s and energy efficiency of 6.66 GOP-W/s on the FPGA, an increase of 1.81 times in computational performance and 1.86 times in energy efficiency compared to the same platform. Compared to unquantized CPU platforms, the computational performance is 0.51 times better, the energy efficiency is 34 times better, and the latency of accelerating a single image is reduced to 383 ms, which allows for better detection performance in the field of target detection and tracking.