IP Core Design Research Articles

Design and Implementation of SoC-based Image Codec IP Cores

Design and Implementation of SoC-based Image Codec IP Cores

Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection

Long-term and effective detection of epileptic seizures is a crucial aspect of epilepsy monitoring and treatment. Addressing the resource overhead issue of wearable epilepsy detection devices, this paper proposes a lightweight hardware implementation scheme for epilepsy detection based on a reusable architecture empirical mode decomposition (EMD) and K-Nearest Neighbors (KNN). Firstly, EMD is used to extract epileptic features from electroencephalogram (EEG), optimized through a reusable architecture design and sawtooth transform to reduce hardware resource usage. Subsequently, a KNN classifier with similarity judgment mechanism is designed to improve the recognition efficiency. Implemented on TSMC 65 nm process, the circuit area is 1.91 mm2, operates at 1 V and 20 MHz, with a power consumption of 4.034 mW. Evaluation on the Bonn EEG dataset yielded a classification accuracy of 96 %, sensitivity of 98 %, and a single detection delay of 1.51 ms. The hardware design offers a simple structure, high accuracy, and low resource consumption, making it suitable for wearable epilepsy detection devices.

Acceleration and implementation of convolutional neural networks based on FPGA

Target detection algorithms are an important technology in the field of computer vision and usually need to be implemented on devices such as CPU or GPU with high computational power. However, traditional CPU are unable to support real-time processing and computations; the power consumption of GPU is relatively high and the application scenarios are limited. FPGA, with their high throughput rate, high power efficiency and reconfigurability, are the best platform for research on hardware acceleration of target detection algorithms. Therefore, how to implement efficient target detection algorithms on embedded devices is an important challenge. A method for YOLOv4-Tiny object detection algorithm accelerator based on FPGA is proposed and demonstrated in this paper. In this design, an optimization strategy is proposed, including the design of IP cores for convolutional computation in HLS, the fusion of batch normalization layers with convolutional layers, dynamic fixed-point 16-bit quantization, loop unrolling double-buffered storage and channel parallel acceleration, which can improve the computational performance and efficiency of the target detection algorithm. The YOLOv4-Tiny target detection algorithm was deployed on an FPGA development board, and experimental results showed that it achieved a computational performance of 18.32 GOP/s and energy efficiency of 6.66 GOP-W/s on the FPGA, an increase of 1.81 times in computational performance and 1.86 times in energy efficiency compared to the same platform. Compared to unquantized CPU platforms, the computational performance is 0.51 times better, the energy efficiency is 34 times better, and the latency of accelerating a single image is reduced to 383 ms, which allows for better detection performance in the field of target detection and tracking.

HLS‐based swarm intelligence driven optimized hardware IP core for linear regression‐based machine learning

AbstractLinear Regression (LR), as one of the essential Machine Learning (ML) models, incurs massive data crunching during the training phase based on many data points. Considering the computationally intensive nature in the LR models, an optimized dedicated hardware IP core design can be very effective. This paper proposes the following novelties: (a) an optimized hardware IP core design of linear regression‐based machine learning model using high‐level synthesis (HLS). More specifically, independent application specific datapath architectures of hardware IP for computing optimal bias and intercepts and cost function in LR‐ML are presented here; (b) an optimized hardware IP core design of LR based ML model by deducing dependency graph from its corresponding mathematical foundation; (c) register transfer level (RTL) design, using HLS, of the optimized LR based ML hardware IP core for computing cost function; (d) linear regression IP core design using multi‐layered tree‐height transformation (THT) and swarm intelligence based architectural exploration for optimized HLS design.

FPGA implementation of QUasi-Affine TRansformation evolutionary algorithm

The QUasi-Affine TRansformation Evolutionary (QUATRE) algorithm, a new intelligence optimization algorithm, has been widely used in many optimization fields. In this paper, a hardware-based QUATRE algorithm is designed and implemented on a field-programmable gate array (FPGA). To facilitate the implementation of the QUATRE algorithm on hardware, this paper simplifies the co-evolutionary matrix generation process. Compared with the original QUATRE algorithm, the simplified QUATRE algorithm may reduce latency and resource occupation. The Vivado High-Level Synthesis (HLS) design tool is used to complete the IP core design of the QUATRE algorithm. Through the benchmark function test under different population sizes, compared with the QUATRE algorithm implemented by software, both the running speed and optimization performance of the QUATRE algorithm implemented by hardware are significantly better than the former. Compared with the GA, DE, and PSO algorithms implemented by hardware, the QUATRE algorithm also shows strong competitiveness.

Convolutional neural network-based lightweight hardware IP core design for EEG epilepsy prediction

Epilepsy is one of the most common neurological disorders. In order to realize a portable and wearable epilepsy prediction device, a lightweight hardware IP core is proposed for EEG epilepsy prediction. The scheme first analyzes the epileptic EEG signal and extracts the time-frequency feature maps of interictal and preictal EEG signals. Then it reduces the network parameters using the single-channel approach to reduce the number of neurons and network complexity, and trains the lightweight epilepsy prediction convolutional neural network by combining the time-frequency feature maps. Finally, a hardware convolutional layer is designed with pipeline function, and it connect 8 layers with feature map buffer to realizes the lightweight EEG epilepsy prediction hardware IP core. Using TSMC 65 nm process, the hardware IP core is functionally verified with 87.9% prediction accuracy. The area is 2.55 mm2 and the power is 4.45 mW. Under 1V & 20 MHz operating conditions, single prediction latency is 3.29 ms and energy efficiency is 0.146 μJ/class.

Design and Implementation of IIC Interface IP Core

With the development of SOC (System on Chip) design technology, IPcore reuse technology and on-chip bus technology, which are the basis of SOC design technology, have attracted wide attention from the society. IP core reuse technology can save repetitive work and greatly speed up chip development. At present, China's large-scale SOC design uses more foreign IP cores, which are expensive. IIC(Inter-integrated Circuit) interface is an important peripheral interface in AMBA (Advanced Microcontroller Bus Architecture) bus. It is used for communication between CPU and peripheral devices, and can be used in embedded, radio frequency communication and other fields. Therefore, designing an IIC interface IP has great use value.

Design and Implementation of an Efficient Hardware Coprocessor IP Core for Multi-axis Servo Control Based on Universal SoC

The multi-axis servo control system has been extensively used in industrial control. However, the applications of traditional MCU and DSP chips in high-performance multi-axis servo control systems are becoming increasingly difficult due to their lack of computing power. Although FPGA chips can meet the computing power requirements of high-performance multi-axis servo control systems, their versatility is insufficient, and the chip is too costly for large-scale use. Therefore, when designing the universal SoC, it is better to directly embed the coprocessor IP core dedicated to accelerating the multi-motor vector control current loop operation into the universal SoC. In this study, a coprocessor IP core that can be flexibly embedded in a universal SoC was designed. The IP core based on time division multiplexing (TDM) technology could accelerate the multi-motor vector control current loop operation according to the hardware–software coordination scheme proposed in this study. The IP was first integrated into a universal SoC to verify its performance, and then the FPGA prototype verification for the SoC was performed under three-axis servo control systems. Secondly, the ASIC implementation of the IP was also conducted based on the CSMC 90 nm process library. The experimental results revealed that the IP had a small area and low power consumption and was suitable for application in universal SoC. Therefore, the cheap and low-power single universal SoC with the coprocessor IP can be suitable for multi-axis servo control.

Design of IP core based on AMBA bus

Design of IP core based on AMBA bus

Design of universal convolutional layer IP core based on FPGA

Design of universal convolutional layer IP core based on FPGA

Pipeline architectures of Three-dimensional daubechies wavelet transform using hybrid method

<span>The application of three-dimensional (3-D) medical image compression systems uses several building blocks for its computationally intensive algorithms to perform matrix transformation operations. Complexity in addressing large medical volumes data has resulted in vast challenges from a hardware implementation perspective. This paper presents an approach towards very-large-scale-integration (VLSI) implementation of 3-D Daubechies wavelet transform for medical image compression. Discrete wavelet transform (DWT) algorithm is used to design the proposed architectures with pipelined direct mapping technique. Hybrid method use a combination of hardware description language (HDL) and G-code, where this method provides an advantage compared to traditional method. The proposed pipelined architectures are deployed for adaptive transformation process of medical image compression applications. The soft IP core design was targeted on to Xilinx field programmable gate array (FPGA) single board RIO (sbRIO 9632). Results obtained for 3-D DWT architecture using Daubechies 4-tap (Daub4) implementation exhibits promising results in terms of area, power consumption and maximum frequency compared to Daubechies 6-tap (Daub6).</span>

2D-CWT IP core design and implementation for fringe pattern analysis

In order to meet the demand of high-speed or real-time analysis for digital interferograms, an advanced hardware accelerated method based on the field programmable gate array (FPGA) is proposed by using the two-dimensional continuous wavelet transform (2D-CWT) technique. In this paper, a 2D-CWT IP core is designed and implemented. It consists of a digital interferograms acquisition module, an interferograms data buffer module, a configuration module, a 2D-CWT operation module, and an output module. When the mother wavelet is selected, e.g., the Morlet wavelet, and the scale factors and rotation angles are setting, the spectrums of fringe patterns are obtained in the 2D-CWT operation module and transferred to the computer through the output module for further processing. Then, the phase distribution of the interferogram is extracted by using the wavelet ridge detection algorithm. Real experiments results show that the 2D-CWT IP core analysis method can reduce the time of phase extraction, and verify the validity and effectiveness of the proposed method.

UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core

The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.

UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE

The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.

Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware

A novel approach for obfuscated JPEG compression/decompression (CODEC) IP core design methodology, suitable for use in re-usable IP core designs, is presented. This incorporates structural obfuscation for architecture or structure hiding from an adversary in order to maximize the complexity against reverse engineering. Additionally, the proposed methodology performs the entire compression and decompression through a single dedicated hardware IP core. To obtain a lightweight (low cost version) of the proposed obfuscated JPEG CODEC IP, particle swarm optimization driven design space exploration is employed. Results of the proposed low cost, obfuscated JPEG CODEC IP core design when compared to un-protected (un-obfuscated) design yielded enhancement in strength of obfuscation of 76%, as well as reduction of 5% compared to un-optimized design.

The Design of IP Core for LCD Controller Based on SOPC

In this paper, it introduces the design and implementation of custom IP core for liquid crystal display (LCD) controller based on system on a programmable chip (SOPC) technology and Verilog hardware description language (HDL). The IP core can be put up as a general-purpose peripheral module to the Avalon Bus, communicating with the NIOS II through registers, and the underlying sequential logic for communicating with the external LCD liquid crystal module is automatically completed by the module. The driver does not need to care about the details of the underlying timing, it only needs to implement the read and write operations of the LCD data through register access, thus achieve the purpose of controlling the display content of the LCD. In addition to reducing the complexity of driver development, the design can also take full advantage of the parallel operation of hardware logic to improve the execution efficiency of the entire system and the throughput of processing tasks, especially in some occasions where high-speed image real-time processing is required. Simulations and experiments show that the IP core for LCD controller has good stability, versatility and compatibility.

Design and implementation of template filtering IP core based on FPGA

Design and implementation of template filtering IP core based on FPGA

Design of CAN controller IP core for intercom of phased array antenna

To achieve miniaturized beam steering system for phased array antenna, a Controller Area Network (CAN) controller IP core based on Avalon bus was designed. Function structure of the IP core was given based on CAN2.0B protocol specification, and designs of controller interface logic, bit stream processor, bit timing logic and so on were completed using Verilog HDL language, and its hardware driver and communication software were developed. The reusability of the IP core was demonstrated with the designed SoPC system which integrated the CAN controller IP core, Nios II microprocessor, phase controller IP core and so on. The experimental results show that the system can realize data communication in the actual network reliably and stably. The built-up system based on this module has many of advantages, such as easy expansion, high portability and broad applicability. The IP core can also be used in high-density and compact industrial control equipments.

Reconfigurable CRC IP core design on Xilinx Spartan 3AN FPGA

This paper presents an efficient, reconfigurable, high throughput IP core implementation of a Cyclic Redundancy Check (CRC) chip design on Field Programmable Gate Array (FPGA). The IP core design has the advantage of correcting multiple errors based on the chosen CRC generator polynomial. The design includes both of the CRC encoder and decoder systems to be used for the serial data transmission and reception of the Wireless Transceiver System. VHDL (VHSIC Hardware Description Language) has been used for describing the hardware of the encoder and decoder systems chip. The IP core design can be reconfigured with different code lengths, maximum burst lengths, and CRC types. It also provides high flexibility by processing various different burst types during runtime. We show detailed simulation and implementation results to demonstrate the performance and hardware complexity of our core. The design has been simulated and tested using ISim (VHDL/Verilog). Spartan 3AN FPGA starter kit from Xilinx has been used for downloading the design into Xilinx chip.

Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems

The tremendous increase in the computing capacity of the embedded architectures has led to widespread deployment of embedded applications. These applications generally exhibit similar patterns in their specification such as filters in which multiply and accumulate operations are repetitive. If such patterns are identified and used for the system design, trade-off between the area and delay can be achieved. This paper proposes a new methodology which allows to implements a design by retrieving similar patterns known as graph isomorphs and interfaces them as HW accelerators in the system-on-chip design flow. An effective algorithm that converges in polynomial time has been proposed to find such similar subgraphs. In the next phase of the design flow, an algorithm has been proposed which performs the scheduling of clusters and minimizes the time overhead. All algorithms have been written in python for parsing the data flow description and test the correctness of the proposed work. The proposed design flow has been applied to five different programs which are sine, cosine, exponent, matrix multiplication and discrete cosine transform (DCT). These have been described as a data flow graph and have been used for results comparison. An estimation table showing the HW and SW parameter of the data flow operators has been developed for timing and area analysis of the programs. The work is an effort to show the clustering and scheduling of a standalone specification which is mapped on static reconfigurable fabric. Reconfigurable computing systems (RCS) are a popular platform for embedded computing applications as they offer a wide exploration in the design space by allowing HW, SW or HW–SW (hybrid) implementation depending on computational demand and resource requirement. These systems have inspired the designers to find new frameworks for achieving the optimized system characteristics under the given constraints. Any static or dynamic HW hardware optimization in an application can be proposed, implemented and easily verified on the chip. The results presented show the comparison of the proposed approach with SW and HW implementation of DCT design on the Xilinx ML507 board. HW timer has been used to find the execution of each implementation. The experimental verification of the proposed algorithms shows that static IP core design flow gives better results.