IP Blocks Research Articles

Interconnect and communication synthesis for distributed register-file microarchitecture

Distributed register-file microarchitecture (DRFM), which comprises multiple uniform blocks (called islands), each containing a dedicated register file, functional unit(s) and data-routing logic, has been known as a very attractive architecture for implementing designs with platform-featured on-chip memory or register-file IP blocks. In comparison with the discrete-register-based architecture, DRFM offers an opportunity of reducing the cost of global (inter-island) connections by confining as many of the computations to the inside of the islands as possible. Consequently, for DRFM architecture, two important problems to be solved effectively in high-level synthesis are: (problem 1) scheduling and resource binding for minimising inter-island connections (IICs) and (problem 2) data transfer (i.e. communication) scheduling through the IICs for minimising access conflicts among data transfers. By solving problem 1, the design complexity because of the long interconnect delay is minimised, whereas by solving problem 2, the additional latency required to resolve the register-file access conflicts among the inter-island data transfers is minimised. This work proposes novel solutions to the two problems. Specifically, for problem 1, previous work solves it in two separate steps: (i) scheduling and (ii) then determining the IICs by resource binding to islands. However, in this algorithm called DFRM-int, the authors place primary importance on the cost of interconnections. Consequently, the authors minimise the cost of interconnections first to fully exploit the effects of scheduling on interconnects and then to schedule the operations later. For problem 2, previous work tries to solve the access conflicts by forwarding data directly to the destination island. However, in this algorithm called DFRM-com, the authors devise an efficient technique of exploring an extensive design space of data forwarding indirectly as well as directly to find a near-optimal solution. By applying this proposed synthesis approach DFRM-int+DFRM-com, the authors are able to further reduce the IICs by 17.9%, compared with that by the conventional DRFM approach, even completely eliminating register-file access conflicts without any increase of latency.

Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications

The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional NoCs (Network on Chip) are not optimal for dataflow applications with large amount of data. On the opposite, point to point communications are designed from the algorithm requirements but they are expensives in terms of resource and wire. We propose a dedicated communication architecture for image analysis algorithms. This communication mechanism is a generic NoC infrastructure dedicated to dataflow image processing applications, mixing circuit-switching and packet-switching communications. The complete architecture integrates two dedicated communication architectures and reusable IP blocks. Communications are based on the NoC concept to support the high bandwidth required for a large number and type of data.

Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs

Given a set of pins and a set of obstacles on routing layers, a multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges within layers and vias between layers and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The ML-OARSMT problem is very important for many very large scale integration designs with pins being located in multiple routing layers that contain numerous routing obstacles incurred from IP blocks, power networks, prerouted nets, etc. As a fundamental problem with extensive practical applications to routing and wirelength/congestion/timing estimations in early design stages, it is desired to develop an effective algorithm for the ML-OARSMT problem to facilitate the design flow. However, there is no existing work on this ML-OARSMT problem. In this paper, we first formulate the ML-OARSMT problem with rectangular obstacles and then identify key different properties of this problem from its single-layer counterpart. Based on the multilayer obstacle-avoiding spanning graph, we present the first algorithm to solve the ML-OARSMT problem. Our algorithm can guarantee an optimal solution for any two-pin net and many multiple-pin nets. Experiments show that our algorithm results in 33% smaller total costs on average than a construction-by-correction heuristic which is widely used for Steiner-tree construction in the recent literature.

Verification of Pin-Accurate Port Connections

Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow.

Evaluating SoC Network Performance in MPEG-4 Encoder

Some previous theoretical studies imply that mesh and other topologies outperform bus as a System-on-Chip (SoC) interconnection. This paper shows how bus performs in a real implementation. We measure and analyze Heterogeneous IP Block Interconnection (HIBI) bus for a multiple clock domain, Multiprocessor System-on-Chip (MPSoC) with an MPEG-4 video encoding application on FPGA. The system is benchmarked with seven different bus clock frequencies and four buffer sizes. A custom hardware monitor is used for the measurements. It is shown that the bus performance is adequate with significantly lower clock frequencies (5 MHz) than other components of the MPSoC (50-100 MHz). Based on the measurements, an estimate for the required bus and CPU frequencies for larger image formats and increased frames/s is shown. In contrast to the theoretical studies, the estimate shows that the bus is still a strong candidate for the SoC interconnection, because it is not the performance-limiting factor.

Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs

Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph, this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any two-pin net and many higher pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works.

System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE) which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.

DASC standards track IP-based design trends

The common engineering practice of decomposing complex problems into a series of simpler subproblems to arrive at effective solutions is mirrored in the electronics industry by the definition and use of IP blocks. Although such blocks were initially fairly simple, the industry has been moving toward the exchange of highly complex, configurable parts such as microprocessors and digital-signal processors. Hence, there's a need for specific IP standards to manage this increased complexity. Although many aspects of the industry could benefit from standardization, three of them are currently being actively addressed: concise, vendor-neutral descriptions of IP characteristics; metrics for IP quality; and IP encryption for protected information exchange. The new standards that the IEEE Design Automation Standards Committee (DASC) is addressing cover both the technical aspects of IP use and the infrastructure for developing sound business models for IP production and distribution.

A full-scale solution to the rectilinear obstacle-avoiding Steiner problem

Routing is one of the important steps in very/ultra large-scale integration (VLSI/ULSI) physical design. Rectilinear Steiner minimal tree (RSMT) construction is an essential part of routing. Macro cells, IP blocks, and pre-routed nets are often regarded as obstacles in the routing phase. Obstacle-avoiding RSMT (OARSMT) algorithms are useful for practical routing applications. However, OARSMT algorithms for multi-terminal net routing still cannot meet the requirements of practical applications. This paper focuses on the OARSMT problem and gives a solution to full-scale nets based on two algorithms, namely An-OARSMan and FORSTer. (1) Based on ant colony optimization (ACO), An-OARSMan can be used for common scale nets with less than 100 terminals in a circuit. An heuristic, greedy obstacle penalty distance (OP-distance), is used in the algorithm and performed on the track graph. (2) FORSTer is a three-step heuristic used for large-scale nets with more than 100 terminals in a circuit. In Step 1, it first partitions all terminals into some subsets in the presence of obstacles. In Step 2, it then connects terminals in each connected graph with one or more trees, respectively. In Step 3, it finally connects the forest consisting of trees constructed in Step 2 into a complete Steiner tree spanning all terminals while avoiding all obstacles. (3) These two graph-based algorithms have been implemented and tested on different kinds of cases. Experimental results show that An-OARSMan can handle both convex and concave polygon obstacles with short wire length. It achieves the optimal solution in the cases with no more than seven terminals. The experimental results also show that FORSTer has short running time, which is suitable for routing large-scale nets among obstacles, even for routing a net with one thousand terminals in the presence of 100 rectangular obstacles.

Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths

Compilers for reconfigurable computers aim to generate problem-specific optimized datapaths for kernels extracted from an input language. In many cases, however, judicious use of preexisting manually optimized IP blocks within these datapaths could improve the compute performance even further. The integration of IP blocks into the compiled datapaths poses a different set of problems than stitching together IPs to form a system-on-chip; though, instead of the loose coupling using standard busses employed by SoCs, the one between datapath and IP block must be much tighter. To this end, we propose a concise language that can be efficiently synthesized using a template-based approach for automatically generating lightweight data and control interfaces at the datapath level.

Scalable Architecture for SoC Video Encoders

Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

An approach that will NoC your SoCs off!

New structured communication fabrics, called networks on chips (NoCs), have emerged for use in SoC designs. The basic concept is to communicate across the chip in the same way that messages are transmitted over the internet today. That is, put a packet-switching network on the chip and send messages back and forth between blocks. Designers have already resolved most of the issues in the Internet domain, so it's just a matter of bringing that knowledge to the chip. Of course, NoC is not a panacea. It does seem appropriate for the multiprocessor SoC platforms that are homogeneous in nature, but the jury is still out on the value of NoC for chips with heterogeneous IP blocks.

HyPE: hybrid power estimation for IP-based systems-on-chip

In this paper, we present a novel power estimation scheme for programmable systems consisting of predesigned datapath and memory components. The proposed hybrid methodology yields highly accurate estimates within short runtimes by combining high-level simulation with analytical macromodeling of circuit characteristics. The kernel of our methodology is a simulation-free power estimation scheme for memoryless datapaths comprising several IP blocks connected in fixed topologies. The outer shell of our hybrid scheme is a functional simulation, which is performed only on the interfaces between memoryless components and memory blocks. This simulation accurately captures the control signals that affect the flow of data and, consequently, the utilization and power dissipation of hardware. Experimental results validate the accuracy and efficiency of our methodology. We applied our static power estimation kernel to signal processing and data encryption datapaths. For designs of up to 576 IP blocks, the average error of our power estimates is 7.3% in comparison with switch-level simulation results. We implemented our hybrid scheme into a power estimation tool, called HYPE, and used it to explore various architectural alternatives in the design of a 256-state Viterbi decoder and a Rijndael encryptor. For designs with about 1 million transistors, our estimator terminates within seconds. Compared with commercial state-of-the-art gate-level power estimators, our proposed methodology is up to 1000 times faster with 5.4% deviation on average.

Low power synthesizable register files for processor and IP cores

In this paper, low power architectures of register files on register-transfer level (RTL) are presented. The proposed architectures are implemented using a standard hardware description language (HDL) and can be synthesized within a commercial semi-custom design flow. The presented register file architectures are ideally suited for synthesizable processor cores or IP blocks. It is shown, that significant power savings of register files can be achieved, if a clock gating scheme for register files different from the one usually applied is used. As an alternative, an architecture with register isolation is presented. The third proposed register file architecture is based on interleaving known from signal processing implementations. Although, interleaving is usually applied to multichannel algorithms, it is shown that this architecture can also be applied to certain single channel cases. Experimental results of all three register file architectures prove that a significant power reduction can be achieved.

A digitally controlled PLL for SoC applications

A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-/spl mu/m standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.

Ic bridge fault modeling for ip blocks using neural network-based vhdl saboteurs

This paper presents a new bridge fault model, suitable for IP blocks, that is based on a multiple layer feedforward neural network and implemented within the framework of a VHDL saboteur cell. Empirical evidence and experimental results show that it satisfies a prescribed set of bridge fault model criteria better than any existing approach. The new model computes bridged node voltages and propagation delay times with due attention to surrounding circuit elements. This is especially significant since, with the exception of full analog defect simulation, no other technique even attempts to model the delay effects of bridge defects. Yet, compared to these analog simulations, the new approach is several orders of magnitude faster and, for a 0.35u cell library, is able to compute bridged node voltages with an average error near 0.006 volts and propagation delay times with an average error near 14 ps. Furthermore, dealing with a concept that has not previously been considered in related research, the new model is validated with respect to deep-submicron technologies for limited gate-count circuit modules.

Guest editor's introduction:] The reuse of complex architectures

Platform-Based Design is an efficient way to design complex system-on-a-chip (SoC)products.PBD moves beyond the reuse of individual IP blocks, to the reuse of complex architectures of hardware and software components organized for a specific application domain. Platforms, along with libraries of predesigned and characterized hardware and software virtual components, enable rapid, low-risk creation of derivative products. Examples of SoC platforms include wireless handset chipsets, digital multimedia devices (such as set-top boxes), automotive systems, and personal digital assistants (PDAs).

Instruction generation for hybrid reconfigurable systems

Future computing systems need to balance flexibility, specialization, and performance in order to meet market demands and the computing power required by new applications. Instruction generation is a vital component for determining these trade-offs. In this work, we present theory and an algorithm for instruction generation. The algorithm profiles a dataflow graph and iteratively contracts edges to create the templates. We discuss how to target the algorithm toward the novel problem of instruction generation for hybrid reconfigurable systems. In particular, we target the Strategically Programmable System, which embeds complex computational units such as ALUs, IP blocks, and so on into a configurable fabric. We argue that an essential compilation step for these systems is instruction generation, as it is needed to specify the functionality of the embedded computational units. In addition, instruction generation can be used to create soft reconfigurable macros---tightly sequenced prespecified operations placed in the reconfigurable fabric.

Interconnection scheme for continuous-media systems-on-a-chip

In this paper, an on-chip interconnection scheme called Heterogeneous IP Block Interconnection (HIBI) is presented. HIBI offers a scaleable and easy to use architecture for system-on-a-chip designs. Its most distinguishing feature is the lack of a central arbiter and specialized arbitration signals. The arbitration is distributed among the connected agents that are made aware of each other's communication requirements. This enables data transmissions with very low latencies and also minimizes the amount of needed signal lines. These features make the scheme a good fit to continuous-media systems transmitting large amounts of streaming data. With the presented interconnection scheme, bus efficiencies greater than 90% have been achieved in several test cases. With the streaming burst transfers and time slot based accesses of HIBI, throughputs of over one data transmission per clock cycle are possible.

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.