Inverter-based Integrators Research Articles

A Σ-Δ Modulator Based on an Inverter-based Integrator with Dynamic Current Switch

This paper presents a low-power high-resolution 3rd-order 1-bit Σ-Δ modulator based on an inverter-based integrator with a dynamic current switch. To reduce the power consumption of the modulator circuit, a dynamic current switch branch is added to form a low-power inverter-based integrator. A 3rd-order 1-bit Σ-Δ modulator is designed in a TSMC 65 nm CMOS technology to verify the effectiveness of the proposed integrator circuit. The prototype Σ-Δ modulator achieves 102.4 dB SNDR, 16.71 Bit ENOB in a 2 KHz signal BW at an Over Sampling Ratio (OSR) of 160, while consuming only 29.5-μW. And the FOMSNDR is 180.7 dB.

A 0.6-V 86.5-dB DR 40-kHz BW Inverter-Based Continuous-Time Delta–Sigma Modulator With PVT-Robust Body-Biasing

This letter presents a low-power continuous-time delta-sigma modulator (CTDSM) that operates at a 0.6 V supply. The loop filter of the CTDSM is realized with inverter-based integrators and negative-R compensation on each integrator’s virtual ground. A body-biasing technique is used for inverters as well as for negative-Rs to ensure robustness against process, voltage, and temperature (PVT) variations. A prototype CTDSM is fabricated in a 28 nm CMOS process, and achieves 83 dB SNDR, 84 dB SNR, and 86.5 dB DR in a 40-kHz bandwidth, while consuming only 33.6 W from a 0.6 V supply. This corresponds to the state-of-the-art Schreier FoM of 177.3 dB.

A 0.4-to-1 V Voltage Scalable $\Delta \Sigma $ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS

This brief presents a two-step hybrid integrator (TSHI) that can operate at a wide supply voltage range, which is demonstrated with a third-order ${\Delta \Sigma }$ analog-to-digital converter (ADC). The proposed TSHI consists of a zero-crossing-detector (ZCD)-based integrator and an inverter-based integrator. In the coarse-integration step, the ZCD-based integrator performs a fast integration without concern for overshoot or detection delay issues. In the fine-integration step, the inverter-based integrator performs the residual integration with high accuracy. Hence, the TSHI provides fast and accurate integration process. In addition, the TSHI supports trade-off between voltage-scalable bandwidth and power consumption for an energy efficient operation of Internet-of-Things sensor nodes, owing to the scalable operation of the ZCD and inverter. The proposed ${\Delta \Sigma }$ ADC is fabricated in a 65-nm LP CMOS process, and the active area is 0.38 mm2. The fabricated ADC operates at supply voltages from 0.4 to 1 V. Depending on the supply voltage and sampling frequency, the power consumption and bandwidth of the ADC can be scaled from 12.7 to $948~{\mu }{\mathrm{W}}$ and from 7.5 to 400 kHz, respectively. The ADC maintains an SNDR higher than 60 dB within the operating supply range.

A 300-<inline-formula> <tex-math notation="LaTeX">$\mu\text{W}$</tex-math> </inline-formula> Audio <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$</tex-math> </inline-formula> Modulator With 100.5-dB DR Using Dynamic Bias Inverter

This paper presents a micropower audio delta-sigma (ΔΣ) modulator for mobile applications. This work employs power-efficient integrators based on the dynamic bias inverter, which consists of a cascode inverter, a floating current source and two offset-storage capacitors. The quiescent current of the inverter is copied from the floating current via offset-storage capacitors and the speed limitation caused by the cascode transistors in the inverter is resolved by using active parasitic compensation. This maximizes both gm/ID ratio and slew rate of the inverter-based integrator, while compensating process, voltage, and temperature (PVT) variations. To verify the effectiveness of the proposed technique, a single-bit third-order ΔΣ modulator is implemented in a 0.18 μm CMOS technology. The prototype modulator achieves 97.7 dB SNDR, 98.6 dB SNR, and 100.5 dB DR in a 20-kHz signal bandwidth, while consuming only 300-μW from a 1.8 V supply. This corresponds to a state-of-the-art Schreier's FoM of 178.7 dB. The results are fully verified under variable supplies and temperatures.

A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS

An ultra-low voltage switched-capacitor (SC) ΔΣ converter running at a record low supply voltage of only 250 mV is introduced. System level aspects are discussed and special circuit techniques described, that enable robust operation at such a low supply voltage. Using a SC biasing approach, inverter-based integrators are realized with overdrives close to the transistor threshold voltage Vth while compensating for process, voltage and temperature (PVT) variation. Biasing voltages are generated on-chip using a novel level shifting circuit, that overcomes headroom limitations due to saturation voltage Vsat. With an oversampling ratio (OSR) of 70 and a sampling frequency (fS) of 1.4 MHz at 250 mV power supply the converter achieves 61 dB SNDR in 10 kHz bandwidth while consuming a total power of 7.5 μW.