Inverted Array Research Articles

Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits

The controllable fabrication of patterned p-type and n-type channels with precise doping control presents a significant challenge, impeding the realization of complementary metal-oxide-semiconductor (CMOS) logic using a single van der Waals material. However, such an achievement could offer substantial benefits by enabling continued transistor scaling and unprecedented interlayer interconnect technologies. In this study, we devise a precise method for two-dimensional (2D) semiconductor substitutional doping, which allows for the production of wafer-scale 2H-MoTe2 thin films with specific p-type or n-type doping. Notably, we extend this approach to the synthesis of spatially selective doped 2H-MoTe2 thin films via a one-step growth method, facilitating the monolithic integration of p-type and n-type semiconductor channels. Leveraging this advancement, we successfully fabricate a chip-sized 2D CMOS inverter array that demonstrates excellent device performance and yield. Collectively, these findings represent a significant stride towards the practical incorporation of 2D semiconductors in very large-scale integration technology.

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

A Reconfigurable SRAM CRP PUF with High Reliability and Randomness

This paper presents a novel reconfigurable SRAM CRP PUF that can achieve high reliability and randomness. In conventional reconfigurable SRAM CRP PUFs, imprecise timing control can produce a biased response output, which is typically attributed to mismatches in the connection of input control signals to the two inverter arrays in the layout floorplan. We propose a timing control scheme along with the addition of an adjunct NMOS transistor to address this issue. This eliminates the connection mismatches for the challenge and word-line inputs to the two inverter arrays. Furthermore, we employ symmetric layout techniques to achieve the randomness of response output. The symmetric arrangement of the two inverter arrays maximizes the inherent random output characteristics derived from process variation. The pre-charge input signal is symmetrically connected to each array to prevent delay mismatches. A 16 × 9-bit reconfigurable PUF array is fabricated by using a 180 nm CMOS process, with a PUF cell area of 1.2 × 104 F2/bit. The experimental results demonstrate an inter Hamming distance of 0.4949 across 40 chips and an intra Hamming distance of 0.0167 for a single chip in 5000 trials. The measured worst bit error rate (BER) is 4.86% at the nominal point (1.8 V, 25 °C). The proposed prototype exhibits good reliability and randomness, as well as a small silicon area when compared to the conventional SRAM CRP PUFs.

Novel approach for modeling and attenuation of power waves in large – scale power systems

In this paper modeling and attenuation of electromechanical power waves in large – scale power systems are discussed. Mathematical model of power wave is derived using Euler – Lagrange equation. The proposed modeling procedure is based on kinetic and potential energies of the system, as well as system’s dissipation power. A novel method for incorporation of spatially dependent power losses into Euler – Lagrange equation is defined as well. The obtained mathematical model is simple for derivation, straightforward and practical for use, so it can easily be applied to derive wave equation of other technical systems or natural phenomena as well, which is an additional advantage compared to the existing models. Based on the developed model, an appropriate control system is proposed. The main idea for control system synthesis is to reduce transmitted waves inside the system. It is shown that the series power line impedance and voltage amplitude have the greatest impact on the wave transmission coefficient. Since unified power flow controller (UPFC) is capable of simultaneously modulating both these parameters, this device is chosen to perform control tasks in proposed operation mode. The effectiveness of the proposed solution has been verified by thorough computer simulations on artificial generator array and IEEE benchmark simplified Australian system. The results show significant power wave reduction. Some future works such as derivation of the mathematical model of inverter array or incorporation of artificial intelligence algorithms in UPFC control system based on transmission coefficient reduction might rely on this work.

Large‐Scale N‐Type FET and Homogeneous CMOS Inverter Array Based on Few‐Layer MoTe2

Abstract2D MoTe2 is regarded as a favorable candidate for semiconductor nanoelectronics integration. Chemical‐vapor‐deposition‐grown MoTe2 usually presents p‐type characteristics. In order to realize basic electronic units like complementary metal‐oxide‐semiconductor (CMOS) inverter, controllable fabrication of p‐ and n‐type transistors at large scale is of vital importance. Here, large‐scale MoTe2 n‐channel field‐effect transistor (n‐FET) arrays are successfully fabricated with seamless coplanar metallic 1T′‐WTe2 contacts to reduce contact resistance. High‐k HfO2 serves as a gate dielectric and its atomic‐layer‐deposition (ALD) process causes an n‐doping effect on the 2H‐MoTe2 channel. The FETs perform typical n‐type characteristics with average electron density and on/off ratio of ≈1.7 × 1013 cm−2 and 2.1 × 104, respectively. Furthermore, large‐scale homogeneous CMOS inverter arrays are fabricated, showing clear logic swing with low power consumption (≈0.4 nW) and high device yield (≈92%). Notably, their voltage transfer characteristics exhibit small hysteresis, and they work well after being kept in air for 16 months, indicating high device stability. The statistical results show that both the n‐FETs and CMOS inverters have high uniformity and reliability in performance. Significantly, this fabrication method is free from transfer processes and compatible with traditional silicon technology. This work paves the way for the application of few‐layer MoTe2 in semiconductor nanoelectronics integration.

High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2.

In thiswork, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS2 and p-MoTe2 grown by the chemical vapor deposition method. In the CMOS device, the n- and p-channel field-effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO2 is used as the gate dielectric. An Al2 O3 seed layer is used to protect the MoS2 from heavily n-doping in the later-on atomic layer deposition process. P-MoTe2 FET is intentionally designed as the upper layer. Because p-doping of MoTe2 results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe2 . An HfO2 capping layer is employed to further balance the transfer curves of n- and p-channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at VDD of 1V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at VDD of 1 V. This work demonstrates the advantage of two-dimensional semi-conductive transition metal dichalcogenides in fabricating high-density integrated circuits.

Plasmonic polymer nanoantenna arrays for electrically tunable and electrode-free metasurfaces

Electrically tunable and electrode-free metasurfaces using plasmonic polymer inverted nanoantenna arrays can operate across the entire spectral range of the material, including the mid-infrared region.

Scalable production of p-MoTe2/n-MoS2 heterostructure array and its application for self-powered photodetectors and CMOS inverters

Recent advances in van der Waals heterostructures have extensively promoted the development of new-generation electronic devices. However, the normally utilized mechanical exfoliation method for preparing two-dimensional semiconductors is not scalable for circuit-level application. Herein, the fabrication and characterization of wafer-scale heterostructure arrays composed of multilayer 2H-MoTe2 and single-layer 2H-MoS2 are demonstrated. Owing to the type-II band alignment facilitating efficient electron–hole separation, the devices fabricated by the p-MoTe2/n-MoS2 heterostructure exhibit an excellent gate-tunable PN diode behavior, with a rectification ratio of over 103 and a self-powered photocurrent with a remarkable on–off ratio of ∼103 at a zero bias voltage. Complementary inverter arrays based on p-MoTe2/n-MoS2 are also demonstrated. The scalable production of p–n junction devices and complementary inverters paves the way for future integrated platforms in photoelectric detection and logic computation.

Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors

l The threshold voltage of the MoS 2 field-effect transistor was controlled by the work function of top gate metal (Au, Cu, Ag, and Al). l The oxidation of the Al gate produced surplus oxygen vacancy (positive charge) and the dipole effect in the HfO 2 dielectric layer. l Transmission electron microscope was employed to explore the thin Al 2 O 3 interlayer in the Al/HfO 2 interface. l The proposed MoS 2 inverter has an optimized inverter switching threshold voltage and DC voltage gain, which possesses significant potential for integrated multistage logic circuits. The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS 2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage ( V th ) for MoS 2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS 2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS 2 inverter arrays with an optimized inverter switching threshold voltage ( V M ) of 1.5 V and a DC voltage gain of 27 at a supply voltage ( V DD ) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS 2 film.

Two-Dimensional Violet Phosphorus: A p-Type Semiconductor for (Opto)electronics.

The synthesis of novel two-dimensional (2D) materials displaying an unprecedented composition and structure via the exfoliation of layered systems provides access to uncharted properties. For application in optoelectronics, a vast majority of exfoliated 2D semiconductors possess n-type or more seldom ambipolar characteristics. The shortage of p-type 2D semiconductors enormously hinders the extensive engineering of 2D devices for complementary metal oxide semiconductors (CMOSs) and beyond CMOS applications. However, despite the recent progress in the development of 2D materials endowed with p-type behaviors by direct synthesis or p-doping strategies, finding new structures is still of primary importance. Here, we report the sonication-assisted liquid-phase exfoliation of violet phosphorus (VP) crystals into few-layer-thick flakes and the first exploration of their electrical and optical properties. Field-effect transistors based on exfoliated VP thin films exhibit a p-type transport feature with an Ion/Ioff ratio of 104 and a hole mobility of 2.25 cm2 V-1 s-1 at room temperature. In addition, the VP film-based photodetectors display a photoresponsivity (R) of 10 mA W-1 and a response time down to 0.16 s. Finally, VP embedded into CMOS inverter arrays displays a voltage gain of ∼17. This scalable production method and high quality of the exfoliated material combined with the excellent optoelectronic performances make VP an enticing and versatile p-type candidate for next-generation more-than-Moore (opto)electronics.

Low-power-consumption CMOS inverter array based on CVD-grown p-MoTe2 and n-MoS2

SummaryTwo-dimensional (2D) semi-conductive transition metal dichalcogenides (TMDCs) have shown advantages for logic application. Complementary metal-oxide-semiconductor (CMOS) inverter is an important component in integrated circuits in view of low power consumption. So far, the performance of the reported TMDCs-based CMOS inverters is not satisfactory. Besides, most of the inverters were made of mechanically exfoliated materials, which hinders their reproducible production and large-scale integration in practical application. In this study, we demonstrate a practical approach to fabricate CMOS inverter arrays using large-area p-MoTe2 and n-MoS2, which are grown via chemical vapor deposition method. The current characteristics of the channel materials are balanced by atomic layer depositing Al2O3. Complete logic swing and clear dynamic switching behavior are observed in the inverters. Especially, ultra-low power consumption of ∼0.37 nW is achieved. Our work paves the way for the application of 2D TMDCs materials in large-scale low-power-consumption logic circuits.

Fabrication and Characterization of Inverted Silicon Pyramidal Arrays with Randomly Distributed Nanoholes

We report the fabrication, electromagnetic simulation and measurement of inverted silicon pyramidal arrays with randomly distributed nanoholes that act as an anti-reflectivity coating. The fabrication route combines the advantages of anisotropic wet etching and metal-assisted chemical etching. The former is employed to form inverted silicon pyramid arrays, while the latter is used to generate randomly distributed nanoholes on the surface and sidewalls of the generated inverted silicon pyramidal arrays. We demonstrate, numerically and experimentally, that such a structure facilitates the multiple reflection and absorption of photons. The resulting nanostructure can achieve the lowest reflectance of 0.45% at 700 nm and the highest reflectance of 5.86% at 2402 nm. The average reflectance in the UV region (250–400 nm), visible region (400–760 nm) and NIR region (760–2600 nm) are 1.11, 0.63 and 3.76%, respectively. The reflectance at broadband wavelength (250–2600 nm) is 14.4 and 3.4 times lower than silicon wafer and silicon pyramids. In particular, such a structure exhibits high hydrophobicity with a contact angle up to 132.4°. Our method is compatible with well-established silicon planar processes and is promising for practical applications of anti-reflectivity coating.

ALD-Based Synthesis of Wafer-Scale Transition Metal Dichalcogenides Towards Nanoelectronics and Optoelectronics Applications

Two-dimensional (2D) transition metal dichalcogenides (TMDs), such as MoS2 and WS2 have been widely studied due to their unique physical and electronic properties even at one atomic layer thickness. Since the first report on the MoS2 field-effect transistor (FET) device [1], great efforts have been made in the past decade to extend the intriguing features of TMDs to practical applications. However, such integration has been severely bottlenecked by the lack of effective approaches to achieve wafer-scale, uniform, crystalline and stoichiometric TMD films.Till now, it is still prevalent to fabricate TMD-based electronic devices using mechanical exfoliation methods. Although single-crystal flakes with least defects can be obtained, the size, thickness and location of the exfoliated TMD flakes are largely uncontrollable, making it unsuitable for large-scale device integration and massive production. So far, various synthetic approaches have been proposed to grow large-area TMD thin films. Chemical vapor deposition (CVD)-based method is one of the major routines to synthesize high-quality monolayer and few-layer TMD flakes [2-4]. For example, in typical CVD processes to grow MoS2, the films can be achieved either by the reduction reaction between the S and MoO3 source powders or by sulfurizing the Mo (or MoOx) films pre-deposited by using physical vapor deposition. However, the nucleation sites in the CVD process are uncontrollable which may lead to the vertical stacking of the MoS2 flakes in triangle shape deteriorating the crystalline properties of the film. On the other hand, the pre-deposited Mo or MoOx film by using e-beam evaporation or sputtering usually suffer from rough surface morphology and unsatisfactory film uniformity which further limit the homogeneity of the large-scale film and device integration.Atomic layer deposition (ALD) is a surface-controlled film fabrication and can provide a possible route towards the synthesis of TMD thin films since the ALD approach follows the layer-by-layer deposition mechanism [5,6]. As compared to the conventional CVD method, ALD can enable precise thickness control on atomic scale and excellent film uniformity as well as good stoichiometry and crystallinity with proper annealing steps. In this work, we employed the ALD-based synthesis method to grow wafer-scale MoS2 and WS2 thin films. Non-toxic MoCl5, WCl5 and hexamethyldisilathiane (HMDST) precursors have been used which are different and superior to those used in previous work. Film characterizations have confirmed the wafer-level uniformity, crystallinity and stoichiometry of the synthesized films. Homogeneous electrical behaviors have also been obtained from the fabricated FET device arrays. In addition, optoelectronic devices such as photodetectors and simple logic gates such as n-type inverter arrays have been demonstrated using the wafer-scale MoS2 FET arrays. Furthermore, we have used the substitutional doping in the ALD process to achieve controllable p-type doping of MoS2 films, which can provide solid basis for the complimentary metal-oxide-semiconductor (CMOS) integrated circuit applications. This work shows that the ALD-based synthesis of the 2D TMD thin films is an attractive approach and has provided a promising platform to further push forward the circuit and system level applications of the TMD materials.

Fast‐Response Inverter Arrays Built on Wafer‐Scale MoS2 by Atomic Layer Deposition

The wafer‐scale integration of the downscaled devices such as transistors based on two‐dimensional (2D) transition metal dichalcogenide (TMD) has attracted great attention in recent years. Such integration is also a significant step towards the system‐level application of these novel low‐dimensional semiconductors. Yet, so far, functional logic circuits based on the 2D TMDs have rarely been reported, largely because of the absence of an effective approach for large‐scale TMD synthesis and the unsatisfactory elementary logic cell performance. In this work, n‐type inverter (NOT gate circuit) arrays have been fabricated based on a wafer‐scale 2D molybdenum disulfide (MoS2) thin film which is grown by atomic layer deposition (ALD). High‐quality crystallinity and excellent wafer‐level uniformity have been successfully achieved. The n‐type inverter array exhibits a fast response with 50 Hz inverse‐frequency. The impact of the device geometry on the inverter performance has also been characterized by designing various width ratio between the load and pull‐down transistors. These results open up an attractive approach to realize the practical application of wafer‐scale 2D MoS2 in logic and circuit systems.

(Invited) 3D Monolithic Integration in Flexible Organic Printed Transistors

Despite the significant enhancements in material properties such as carrier mobility, few attempts have been made to print organic integrated circuits (ICs). The relatively large size of printed features (typically 10 μm – 100 μm) have limited the implementation of organic ICs with reasonable transistor densities. To overcome the limitation, we introduce three-dimensional (3D) integration of inkjet-printed organic transistors and circuits. We fabricated a p-type organic field-effect transistor that is inkjet-printed on top of an n-type organic field-effect transistor with a shared gate joining the two transistors. Based on the common-gate transistor-on-transistor structure, a complementary inverter array is fabricated with a high static noise margin and reliable characteristics. We have further developed 3D integration of a dual-gate NAND technology fabricated by printing technique with a demonstration of flexible logic circuits. The vertical stacking of independent-gate controlled dual gate transistors offers enhanced on-current, lowered sub-threshold swing, increased device stability and density. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs, and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices

Fully inkjet-printed short-channel organic thin-film transistors and inverter arrays on flexible substrates

We report fully inkjet-printed organic thin-film transistors (OTFTs) and inverters with an average channel length of 9 μm and minimized overlap capacitance between gate and source/drain (S/D) electrodes on a flexible plastic substrate. Metal-organic precursor-type silver ink, poly(4-vinylphenol), and 6, 13-bis (triisopropylsilylethynyl)pentacene were used to form the gate and S/D electrodes, the gate dielectric, and the active semiconductor layer, respectively. Well-defined S/D electrodes with narrow width and spacing can be realized by introducing a separate printing process and interdigitated structure with a cartridge that can eject a 1 picoliter volume of ink droplets without any assistant surface treatments or structures. Fully inkjet-printed short channel OTFT arrays presenting an average mobility of 0.065 cm2 V−1 s−1 and on/off ratio of 4 × 103 and inverter arrays exhibiting a voltage gain of 5.5 at a VDD of −30 V and good frequency response were demonstrated.

Vertically Stacked Complementary Organic Field‐Effect Transistors and Logic Circuits Fabricated by Inkjet Printing

Vertically stacked complementary organic field-effect transistors and logic circuits are fabricated by inkjet printing. Based on a common-gate transistor-on-transistor structure, a complementary inverter array is demonstrated with a high static noise margin and reliable characteristics. This study reports a general strategy to continuously increase the transistor density of printed devices.

A New Quantum Number Triangular Array That Defines the Internal Organization of Valence Quarks, the Hadron Quark Model, and the CKM Matrix

Purpose: The Harmonic Neutron Hypothesis, HNH, has demonstrated that many of the fundamental physical constants, including the quarks, are associated with partial harmonic fractional exponents, , of a fundamental frequency, vF. The model has shown that the properties of the quarks are based on a progression of prime number composites. They also fall on three separate power law lines related to integer factors of the Y-intercept, , of a fundamental electromagnetic line which is scaled by the Rydberg constant, R and Planck’s constant. The quark lines are scaled by the quantum number factors {1, 2, 3}, and their Y-intercepts are referred to as nbem. The goal is to present a new proto-quark model in a six-quark inverted triangular array that defines the global organization of the valence quarks, which determines the hadronic quantum numbers, the standard hadron quark model, and the Cabibbo-Kobayashi-Maskawa (CKM) matrix. Methods: The charm, bottom, top quarks are associated with power law line Y-intercept, nbem equal to 1; the strange and down quarks with nbem equal to 2; and the up quark with nbem equal to 3. An inverted equilateral triangular array with three rows arranged from upper row (triangle base) to bottom row (triangle vertex), is associated respectively with nbem numbers 1, 2, and 3. The novelty of our perspective thus defines a new global valence quark organization which supersedes the Standard hadron composite quark model. The quarks are ordered via relative mass, partial fractions, and nbem quantum number. The top row of our inverted triangle includes the c, b, and t quarks from left to right; the middle row depicts the d and s quarks; and the bottom row, the up quark. Results: Our array depicts a quantum generator of the global organization of the valence quarks defining the composite quark model. The vertices of the triangular array are the up quarks, the midpoints are the down quarks. All weak transitions are from a corner to a midpoint or vice versa. The standard 3 by 3 CKM matrix is generated from the new quark triangle with each up type quark (u, c, and t) transforming to each down type (d, s, and b), with their experimental flavor transition magnitudes given. Conclusion: A new quark quantum number, nbem, is an important discovery that generates a new proto-valence quark triangle that secondarily generates the composite quark model and the CKM matrix.

Tristate Inverter Array: A New Technology Development Yield Learning Vehicle Complementing Traditional SRAM Arrays

The SRAM bitcell array has been traditionally used as a yield learning vehicle for new technologies. However, the yield of the SRAM bitcell is susceptible to parametric variations and subtle process defects/variations. In this paper, a new functional array called the tristated inverter array is discussed which is much less susceptible to both parametric variation and subtle process defects while retaining all the useful features of the SRAM array (fail mappability, ease of isolation of fails, regular design). This structure can be used very effectively in yield learning as a complimentary test structure to the SRAM array for learning hard process defects.

Fabrication of Stretchable Single‐Walled Carbon Nanotube Logic Devices

The fabrication of a stretchable single-walled carbon nanotube (SWCNT) complementary metal oxide semiconductor (CMOS) inverter array and ring oscillators is reported. The SWCNT CMOS inverter exhibits static voltage transfer characteristics with a maximum gain of 8.9 at a supply voltage of 5 V. The fabricated devices show stable electrical performance under the maximum strain of 30% via forming wavy configurations. In addition, the 3-stage ring oscillator demonstrates a stable oscillator frequency of ∼3.5 kHz at a supply voltage of 10 V and the oscillating waveforms are maintained without any distortion under cycles of pre-strain and release. The strains applied to the device upon deformation are also analyzed by using the classical lamination theory, estimating the local strain of less than 0.6% in the SWCNT channel and Pd electrode regions which is small enough to keep the device performance stable under the pre-strain up to 30%. This work demonstrates the potential application of stretchable SWCNT logic circuit devices in future wearable electronics.