Inversion Capacitance Research Articles

Enhancing the Tunable Sensitivity of a Near-Ultraviolet to Visible to Near-Infrared Photo Irradiance Sensor Using an Indium Tin Oxide-Aluminum Oxide-Zirconia Aluminum Oxide-Silicon

This study focuses on enhancing the tunable sensitivity of a photo irradiance sensor (PIS) operating in the near-ultraviolet to visible to near-infrared (NUV-VIS-NIR) spectrum using an indium tin oxide-aluminum oxide-zirconia aluminum oxide-silicon oxide-silicon capacitor (hereafter IAZAOS). Unlike other PIS designs such as reverse-biased metal–insulator–semiconductor (MIS) and tunneling MIS, the IAZAOS PIS measures changes in inversion capacitance under strong forward bias with light irradiation. The IAZAOS PIS offers several key advantages over alternative designs. It exhibits high sensitivity, weak bias dependence, low dark current, tunable sensitivity, low power consumption, CMOS process compatibility, simple low-cost manufacturing, and good gate oxide reliability. Under 1 mW/cm2 irradiation at 1 kHz, the inversion carrier concentration reaches approximately 70% saturation. The resolution achieved is 10 nW/cm2 at 1 kHz, with a sensing range spanning from 10 nW/cm2 to 1 W/cm2 across frequencies from 1 kHz to 100 kHz. These performance characteristics surpass those reported for other PIS technologies. Furthermore, the IAZAOS PIS demonstrates a quantum efficiency of about 60% at 405 nm, which surpasses the quantum efficiency of general silicon-based p(i)n diodes. Post-deposition annealing techniques are employed to enhance the sensor’s performance. Dielectric annealing improves the ZrAlOx interface trap and permittivity properties, while conducting oxide annealing enhances indium tin oxide transmission and resistivity. The combination of these treatments results in a high-speed, high-sensitivity, high-resolution, and reliable NUV-VIS-NIR sensing capability for the IAZAOS capacitor-based PIS.

Reliability Analysis on TiN Gated NMOS Transistors

Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.

Proposal and Experimental Demonstration of Ultrathin-Body (111) InAs-On-Insulator nMOSFETs With L Valley Conduction

Ultrathin-body (UTB) (111) InAs-On-Insulator (InAs-OI) n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) are proposed as a new technology booster using the L valley conduction in III–V channels. The performance of the conventional UTB III–V nMOSFETs is limited by the essential band features of the $\Gamma $ valley conduction such as the low density of states, resulting in low inversion capacitance, and the light effective mass ${m}_{z}$ along the confinement direction, resulting in strong thickness fluctuation scattering. The strong confinement of electrons by a combination of (111) surface orientation and UTB InAs-OI structures is expected to transfer the electrons into the L valley with much heavier ${m}_{z}$ than in the $\Gamma $ valley, leading to higher semiconductor capacitance and suppression of thickness fluctuation scattering. We also experimentally demonstrate the UTB (111) InAs-OI nMOSFETs operation with thinning the InAs channels down to 3 nm, realized by the smart-cut and digital etching process. Channel thickness scaling improves both the OFF- and ON-currents by expansion of the effective bandgap. It is shown that the measured mobility increases with decreasing InAs-OI thickness from 4.8 to 4.4 nm, which is attributable to the increase in the electron occupancy in the L valley.

Dual-Material Gate-Drain Overlapped DG-TFET Device for Low Leakage Current Design

In this paper; we propose DMDG-GDOV TFET device structure for low leakage current. Considering the potential benefits of DMDG-TFET, emphasize with Gate Drain Overlap (GDOV) has been simulated with high-k (HfO2) and low-k (SiO2) which results in elevated ON current (ION) as well as less leakage current. The gate region and drain region overlap shows low leakage current as compared to non-overlap gate terminal on drain side in DMDG-TFET. This gate-region on drain-region overlap reduces the electric field in the ambipolar condition and exhausts the carrier in the drain terminal side away from the junction. However, gate electrode overlapped on drain side inevitably enhances the gate-to drain capacitance (CGD) i.e. Miller Capacitance due to increase in overlap capacitance (COV) and inversion capacitance (Cinv). Hence by using high-k dielectric and low-k dielectric deposition over channel region and source-drain region respectively with dual-metal gate technique, the CGD capacitances has been reduced. This CGD further reduces the intrinsic delay by adjusting the gate metal work function of dual metal where ФTgate is (4.3 eV) greater than ФSgate (4.1 eV).

Investigation of interface state density near conduction band edge of 4H-SiC MOSFET based on inversion capacitance and drain-current characteristics

We propose a simple method to evaluate interface state density (Dit) near the conduction band edge of 4H-SiC MOSFETs, which is difficult to observe by conventional methods although it degrades device characteristics. We focus on a capacitance–voltage method with inversion capacitance, applying high voltage to a set reference point where almost all traps are occupied and sweeping downward gradually. Our method is applicable for mass production because of the convenient sequence. We also demonstrate that the device characteristics calculated based on the extracted Dit are in good agreement with the measured characteristics.

Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance

This paper investigates the inversion charge characteristics and quantum-capacitance induced inversion charge loss for In 0.53 Ga 0.47 As negative-capacitance FinFETs (NC-FinFETs) using theoretical calculation corroborated with numerical simulation. Our study indicates that, the boost of inversion charges due to negative capacitance increases with increasing remnant polarization Pr. In addition, the inversion charge boosting for the In 0.53 Ga 0.47 As device is significantly larger than that of the Si (110) device due to the step-like inversion capacitance characteristic stemming from the 2D density-of-states of the In 0.53 Ga 0.47 As device. In other words, the quantum-capacitance induced inversion-charge loss for III-V channel can be mitigated in NCFETs.

Direct observation of inversion capacitance in p-type diamond MOS capacitors with an electron injection layer

The electrical properties of Al2O3/p-type diamond (111) MOS capacitors were studied with the goal of furthering diamond-based semiconductor research. To confirm the formation of an inversion layer in the p-type diamond body, an n-type layer for use as a minority carrier injection layer was selectively deposited onto p-type diamond. To form the diamond MOS capacitors, Al2O3 was deposited onto OH-terminated diamond using atomic layer deposition. The MOS capacitor showed clear inversion capacitance at 10 Hz. The minority carrier injection from the n-type layer reached the inversion n-channel diamond MOS field-effect transistor (MOSFET). Using the high-low frequency capacitance method, the interface state density, Dit, within an energy range of 0.1–0.5 eV from the valence band edge energy, Ev, was estimated at (4–9) × 1012 cm−2 eV−1. However, the high Dit near Ev remains an obstacle to improving the field effect mobility for the inversion p-channel diamond MOSFET.

Study of various technological parameters on the C-Vg and the G-Vg characteristics of MOS structures

This paper was devoted to study the effects of some technological parameters (gate, oxide and doping density Na on the electrical properties of MOS structures. The conductance and capacitance were determined from a proposed admittance model. Results showed a frequency dispersion of C-Vg and G-Vg curves in inversion regime. This modeling takes into account the influence of series and parallel resistances (Rs, Rp), thickness of oxide layer, the work function of gate electrode and the doping density (Na). The C-Vg and G-Vg characteristics have been simulated at high frequency (100 kHz-1 MHz).With increasing frequency, the inversion capacitance is decreased whereas the conductance is strongly increased. A degradation of their shapes is shown in the operating accumulation and depletion modes. The accumulation capacitance seems to be strong for titanium oxide (TiO2) and for the oxide thickness is very small. Interestingly, the change of metal gate causes C-Vg shifting and variation of the values of the flat band and threshold voltages. In the inversion mode, the C - Vg and G-Vg decreases with the increase of the doping density (Na). There is a shift of the flat-band and threshold voltage (Vfb,Vth) when Na increase. Excellent agreement was observed between the calculated and the measured C-Vg curves obtained at high frequency.

Lateral Non-Uniformity Reduction by Compensatory Metal Embedded in MOS Structure with Ultra-Thin Anodic Oxide

In order to reduce the degradation caused by lateral non-uniformity (LNU) of gate oxides in metal-oxide-semiconductor (MOS) devices, a method to ameliorate the lateral oxide uniformity was proposed. By adopting the anodic oxidation compensation (ANO-compensation) technique to compensate the embedded aluminum layer, significant uniformity improvements were found in capacitance per unit area-voltage (C’-V) and current density-voltage (J-V) characteristics, and the percentage dispersions of capacitance per unit area and current density in accumulation regime also give the support to uniformity improvement. Besides, the outcomes of reliability tests also evidence that the LNU is reduced. Hence, with the advantages of superior oxide uniformity, the enhanced response in inversion capacitance was observed. At last, nitrate solution is used for validating the advantage of anodic oxidation compensation, and the J-V and C-V characteristics show that anodic oxidation compensation is necessary for fabricating reliable MOS-based devices.

Lateral Non-Uniformity Reduction by Compensatory Metal Embedded in MOS Structure with Ultra-Thin Anodic Oxide

Lateral non-uniformity (LNU) of gate dielectric has been a serious problem in modern metal-oxide-semiconductor (MOS) devices [1], [2]. It was found the LNU became more severe after adopting the post-metalization annealing (PMA) due to possible spiking of metal. The interface of metal and gate dielectric was believed to be uneven after PMA. In this work, a method to ameliorate the lateral uniformity in MOS capacitors was proposed. By utilizing the anodic oxidation compensation technique to form a compensatory aluminum layer embedded in MOS structure, obvious improvement in lateral oxide uniformity was observed. The schematic of anodic oxidation compensation is shown in Fig. 1. Accordingly, two batches of MOS capacitors with ultra-thin anodic oxide with equivalent oxide thickness (EOT) ranging from 2 nm to 3.4 nm was prepared for comparison. One is denoted as MOS (MOS stands for the simple Al/SiO2/Si(p) structure), while the other one is denoted as EAMOS (EAMOS stands for Al/Al2O3/Al/SiO2/Si(p) structure with compensatory embedded aluminum). From our previous work, it is known that the electrical characteristics of MOS capacitors in accumulation regime are area-dependent [3]. Hence, the electrical characteristics in accumulation regime are practical for examining the degree of LNU. Fig. 2 shows the current-voltage (I-V), current density-voltage (J-V) and capacitance per unit area-voltage (C’-V) characteristics of both devices. It is obvious that the area-dependence is applied much better in EAMOS devices, which clearly indicates the reduction of LNU. Furthermore, in order to verify the uniformity improvement in whole samples, the percentage dispersions of different device areas of current density and capacitance per unit area in accumulation regime with varied EOT’s are illustrated in Fig. 3. In Fig. 3, for each EOT, the quantity of dispersion of MOS devices is larger than the value of EAMOS devices. Fig. 3(a) shows that the average percentage dispersion of MOS devices for capacitance per unit area with various EOT’s is 3.95%, which is larger than the value of 2.28% of EAMOS devices. Fig. 3(b) shows that the average percentage dispersion of MOS devices for current density with various EOT’s is 90.33%, whereas the value of EAMOS devices (27.7%) is much smaller. These results further serve as the evidences of lessening of LNU. In addition, the breakdown behaviors also point out the improvement in oxide uniformity. Fig. 4 shows the characteristics of time-zero dielectric breakdown (TZDB) of thirteen identical devices for both MOS and EAMOS samples. The values of breakdown voltage for EAMOS devices are more consistent (-4 V to -5 V), while the values for MOS devices range from -2.5 V to -5 V, which are comparatively divergent. Furthermore, currents at -2 V and -8 V are more congruous for EAMOS devices. Consequently, these results give another support to the improved oxide uniformity. Finally, benefited from the reduction of LNU, the lateral distribution of vertical electric field must be more uniform. So when biasing at inversion regime, we believed that the induced minority carriers would distributed more uniform in lateral direction. Therefore, the lateral electric field induced by the non-uniformity of minority carriers would be attenuated. So relieved from the disturbance of lateral Coulomb force, the response of minority carriers to the small signal of gate voltage is believed to be more significant in the EAMOS devices than the MOS devices. Fig. 5 shows the capacitance-voltage (C-V) characteristic of both MOS and EAMOS devices with EOT of 3.4 nm and various frequencies. It is obvious that the frequency response of inversion capacitance is more significant for the EAMOS device than the MOS device. This outcome is consistent with the explanation given above, and it is of use for the circuit design consideration in MOS-based devices. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. NSC 102-2221-E-002-183-MY3 and MOST 103-2622-E-002-031.

Quantization effects on the inversion mode of a double gate MOS

We investigate the quantization effects on the gate capacitance and charge distribution of a double gate MOSFET using a self-consistent solution of Poisson and Schrödinger equations of the industry standard simulation package Silvaco. Quantization effects on the gate C–V are simulated by varying the electron and hole effective masses. We notice that the inversion capacitance value decreases as the effective mass goes below 0.1mo and the shape of the C–V curve changes to step like in the inversion. We also notice that the inversion switches from surface inversion to volume inversion for low effective mass, and the quantization effect (step like shape) in C–V and volume inversion in charge profile happen at the same effective mass.

Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations.

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (Cgd) because of the increase in the overlap capacitance (Cov) and inversion capacitance (Cinv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (Cgg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (φgate) and φoverlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower Cgg divided by the on-state current (Ion), i.e., Cgg/Ion. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.

III-V Tri-Gate Quantum-Well Mosfet for 10nm Technology and Beyond

With sub-10nm node technology approaching fast, counteracting short channel effects (SCEs), sub-threshold conduction, reducing transistor off-current and gate leakage current have become aspects of real concern. Integration of III-V semiconductors in multigate device architectures has become a topic of intense research and study for low power logic implementation [1]. Multigate device architectures like FinFETs, GAA FETs provide better control over channel carrier accumulation and improved short channel performance over planar structures. Recently, In0.53GA0.47As Quantum-Well (QW) Tri-Gate MOSFET with bi-layer high-k dielectrics of Al2O3/HfO2 has been reported with channel width and height scaled down to 30nm and 20nm respectively and gate length scaled down to 60nm [2]. In this work, we present a simulation study of inversion Capacitance-Voltage (C-V) and Threshold (VTH) characteristics of a III-V tri-gate device (Fig.1 inset) using self-consistent modeling. The device structure used for modeling in this study incorporates 2nm Al2O3 with In composition kept at 0.7 in the undoped InGaAs QW channel. The In0.52Al0.48As back barrier thickness is kept at 60nm. In this study TiN has been used as the gate metal. In all these studies, temperature is considered to be fixed at 300K. Finite Element Method (FEM) has been used to solve Schrodinger-Poisson equations in a coupled manner applying proper boundary conditions, using COMSOL Multiphysics and MATLAB, taking into account wave function penetration and other quantum mechanical effects. 2D Schrodinger equation is solved using effective mass approximation and open boundary condition to determine electron wave functions and eigen states in the quantum well. Using carrier wave functions in the tri-gate channel, inversion carrier concentration is determined by applying 1D density of states and Fermi-Dirac distribution function. The effect of fixed oxide charges, interface trap charges and oxide border trap charges is not taken into account. The developed simulator is also benchmarked with the simulation results obtained for a III-V GAA nanowire transistor [3]. A quantum definition of threshold voltage for multigate FETs is available in literature [4]. According to this definition, the threshold voltage can be presented as a combination of classical and quantum terms. Here, peak electron concentration npeak(x,y) and average electron concentration navg are used to define threshold voltage of the device. At threshold point, the profile of npeak(x,y)/navg would show a change in slope which results from shift in carrier accumulation as device operation moves from subthreshold to inversion mode [4]. In this study, same definition of threshold voltage has been used. The simulation reveals strong carrier accumulation at the corners of the oxide/semiconductor interface which is expected for multigate device structures (Fig. 1). The simulation also reveals strong subband quantization in the QW channel (Fig. 2). Occupied subbands below the Fermi level contribute to the carrier concentration. As the device dimension is shrunk, volume inversion effect becomes more and more significant and carriers begin to accumulate at the middle portion of the tri-gate channel. This phenomenon leads to an increase in carrier concentration in the middle portion of the QW fin as channel dimension is scaled (Fig. 3). This phenomenon shifts channel formation towards the middle portion of the tri-gate QW fin. Simulation also reveals higher inversion capacitance at lower In composition in the channel which may be attributed to higher density of states effective mass at lower In composition (Fig. 4). Although variation of top gate oxide thickness reveals effect on inversion capacitance, the threshold voltage remains mostly unchanged with top gate oxide thickness. Study of variable channel dimension while keeping WFin=HFin reveals lower carrier accumulation in the device cross section per unit channel length which may lead to lower inversion capacitance with lower channel dimension (Fig. 5). Lowering channel dimension results in stronger quantum confinement and subband splitting which eventually leads to an increase in threshold voltage (Fig. 6). Lowered In composition in the channel also increases threshold voltage of the device (Fig. 6). In this work, a simulation study of a III-V tri-gate quantum well device for 10nm technology and beyond is presented. The outcome of this work would be useful in the implementation of III-V multigate device structures for high speed and low power logic applications.

(Invited) Preparation of GaSb Surface for Low Interfacial Trap Density MOS Capacitors

High mobility III-V compound semiconductors have been extensively investigated recently for future complementary metal-oxide-semiconductor (CMOS) applications. GaSb, which has high electron and hole mobilities as well as a narrow bandgap is an attractive material for future high-speed and low-power integrated circuits. Due to the easy formation of native oxides, i.e. SbOx, GaOx, and elemental Sb clusters on GaSb surface, Fermi-level pinning and high interfacial trap density (Dit) has been a major obstacle to high quality MOS devices. In this talk, we will present both in-situ and ex-situ techniques to prepare GaSb surface and realize metal-oxide-semiconductor capacitors (MOSCAPs) with low interfacial trap density. The i n-situ approach is conducted in a system equipped with a high vacuum sample transfer tube that connects a molecular beam epitaxy (MBE) tool and an atomic layer deposition (ALD) chamber. A native oxide-free surface can thus be preserved for high-κ dielectrics deposition. HfO2/Al2O3/GaSb MOSCAPs fabricated on Sb-stabilized surface exhibit clear inversion behavior at low frequency and good modulation of the Fermi level across the whole GaSb band gap. Modulation of the inversion capacitance at 100 kHz reaches 30 %, suggesting low Dit as well as low bulk trap density at the interface. The Dit extracted by the conductance method is about 7.6×1011 cm-2eV-1 near the valence band. As to the ex-situ process, air-exposed GaSb samples are treated by hydrogen plasma at room temperature prior to ALD dielectrics. Under optimized plasma treatment conditions, similar C-V characteristics and gate leakage current of HfO2/Al2O3/GaSb MOSCAPs to those of the in-situ ones are observed. Modulation of the inversion capacitance at 100 kHz even reaches 36 % and the Dit near the valence band is as low as 6.0×1011 cm-2eV-1. Structural and chemical analyses of the dielectric/semiconductor interface by high-resolution transmission electron microscopy (HRTEM) and x-ray photoelectron spectroscopy (XPS) show that the in-situ MOSCAPs have a native oxide-free interface, while hydrogen plasma treatment results in the formation of GaOx, which may serve to passivate defects and dangling bonds at the GaSb surface

Synthesis, characterization and radiation damage studies of high-k dielectric (HfO2) films for MOS device applications

The current trend in miniaturization of metal oxide semiconductor devices needs high-k dielectric materials as gate dielectrics. Among all the high-k dielectric materials, HfO2 enticed the most attention, and it has already been introduced as a new gate dielectric by the semiconductor industry. High dielectric constant (HfO2) films (10 nm) were deposited on Si substrates using the e-beam evaporation technique. These samples were characterized by various structural and electrical characterization techniques. Rutherford backscattering spectrometry, X-ray reflectivity, and energy-dispersive X-ray analysis measurements were performed to determine the thickness and stoichiometry of these films. The results obtained from various measurements are found to be consistent with each other. These samples were further characterized by I–V (leakage current) and C–V measurements after depositing suitable metal contacts. A significant decrease in the leakage current and the corresponding increase in device capacitance are observed when these samples were annealed in oxygen atmosphere. Furthermore, we have studied the influence of gamma irradiation on the electrical properties of these films as a function of the irradiation dose. The observed increase in the leakage current accompanied by changes in various other parameters, such as accumulation capacitance, inversion capacitance, flat band voltage, mid-gap voltage, etc., indicates the presence of various types of defects in irradiated samples.

The Ag Nanoparticles/TiO2 Thin Film Device for Enhanced Photoconduction and Role of Traps

Glancing angle deposition technique was carried out to synthesize silver (Ag) nanoparticles (NPs) on titanium dioxide (TiO2) thin film (TF) over n-type Si substrate. The presence of Ag NPs on the TiO2 TF enhanced the photoconduction as compared to bare TiO2 TF. The maximum photosensitivity of the Ag NPs/TiO2 TF (plasmonic) device was recorded ∼700 times than that of the bare TiO2 TF at −3 V. The devices were UV sensitive and maximum internal gain for the plasmonic device was calculated to be ∼210 at 380 nm. The inversion capacitance of the plasmonic devices responded with a.c. signal efficiently as compared to bare TiO2 TF. Under applied sweeping top electrode voltage Vs ±10 V, the corresponding maximum memory window of 4.5 V was observed for plasmonic device in its capacitance (C)–voltage (V) curve. The Ag NPs-patterned TiO2 TF device possessed higher impedance than that of the bare TiO2 TF-based device.

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

AbstractHigh‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of InxGa1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 1023 m−3, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 1023 m−3, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.

Simulación TCAD para un MOSFET de silicio en aislante, ultra fino con óxido enterrado y completamente agotado: una comparación entre COMSOL y Sentaurus

En el presente trabajo, se desarrolla un modelo para simular un dispositivo MOSFET de silicio en aislante, ultra delgados con oxido enterrado (20m) y agotados completamente con SiO2 (5nm) como compuerta. El software que se usa es TCAD-Sentaurus. Se desarrollaron simulaciones DC para estudiar el comportamiento del voltaje de encendido y la transconductancia. Además, se desarrollaron simulaciones AC para estudiar la capacitancia y carga de inversión. Los resultados fueron comparados con un trabajo previo en el que se usó como simulador al programa COMSOL-Multiphysics. Los resultados obtenidos son muy similares entre ambos trabajos. Sin embargo, Sentaurus ofrece características más interesantes como introducir modelos más reales para los mecanismos físicos de dispositivos complejos.

Visible Light Sensor Based on Metal-Oxide-Semiconductor Structure

We present results for the effect of visible and UV light on the capacitance-voltage characteristics of a p-type Si based Metal-Oxide-Semiconductor ring-dot structure. It is shown that the structure can be used as a low cost sensor that is simple and easy to manufacture. The sensor can be used to measure visible and UV light intensity or as a light switch. The output signal is change of the inversion capacitance under light illumination at a given bias. The device power consumption is very low and the output signal is independent of the temperature.

Effect of trapped electrons in ultrathin SiO2 on the two-state inversion capacitance at varied frequencies of metal-oxide-semiconductor capacitor

Two-state inversion capacitances of a metal-oxide-semiconductor capacitor (MOSCAP) at varied AC frequencies after negative/positive constant voltage stress (negative/positive CVS) treatments are investigated. When the device was biased into inversion, a low/high inversion-capacitance state (set state/reset state) was achieved after the negative/positive CVS treatments with/without a few trapped electrons in the ultrathin SiO2 layer. The inversion capacitances of set states were frequency independent, whereas those of reset states increased with the decreasing frequencies. It is different from the general characteristics of an MOSCAP whose inversion capacitances disperse at low frequencies. For this observed finding of the two-state inversion capacitances at varied frequencies, a mechanism of trapped-electrons-induced screening effect on the inversion electrons is proposed. The number of the trapped electrons in the SiO2 layer affects the number of the inversion electrons, and thus dominates the values of the inversion capacitances. Besides, simulation curves of the inversion capacitances of set states are demonstrated. They are fitted well with the experimental data utilizing the mechanism we proposed. This work investigates further into the influence of the trapped electrons in the ultrathin SiO2 layer on the inversion capacitance response.