Dual-Material Gate-Drain Overlapped DG-TFET Device for Low Leakage Current Design

Abstract

In this paper; we propose DMDG-GDOV TFET device structure for low leakage current. Considering the potential benefits of DMDG-TFET, emphasize with Gate Drain Overlap (GDOV) has been simulated with high-k (HfO2) and low-k (SiO2) which results in elevated ON current (ION) as well as less leakage current. The gate region and drain region overlap shows low leakage current as compared to non-overlap gate terminal on drain side in DMDG-TFET. This gate-region on drain-region overlap reduces the electric field in the ambipolar condition and exhausts the carrier in the drain terminal side away from the junction. However, gate electrode overlapped on drain side inevitably enhances the gate-to drain capacitance (CGD) i.e. Miller Capacitance due to increase in overlap capacitance (COV) and inversion capacitance (Cinv). Hence by using high-k dielectric and low-k dielectric deposition over channel region and source-drain region respectively with dual-metal gate technique, the CGD capacitances has been reduced. This CGD further reduces the intrinsic delay by adjusting the gate metal work function of dual metal where ФTgate is (4.3 eV) greater than ФSgate (4.1 eV).