Invalid Blocks Research Articles

Fast motion estimation based on adaptive search range adjustment and matching error prediction

This work presents fast motion estimation (ME) by using both an adaptive search range adjustment and a matching error prediction. The basic idea of the proposed scheme is based on adjusting a given search range adaptively and predicting a block matching errors effectively. The adaptive search range adjustment is first performed by analyzing the contents of a scene. Next, the total block matching error is estimated by using partial errors of sub-sampled blocks to eliminate invalid blocks earlier for ME. In order to evaluate the proposed scheme, several baseline approaches are described and compared. The experimental results show that the proposed algorithm can reduce the computational cost more than 81% for ME at the cost of 0.01 dB image quality degradation versus the conventional PDE algorithm1. The main contributions of the proposed approach are that 1) it can reduce the computational cost considerably; 2) it can be applied to conventional PDE algorithms without significant changes; and 3) it can be a useful tool for fast ME in the consumer electronics-related field.

New sorting-based lossless motion estimation algorithms and a partial distortion elimination performance analysis

In video encoding, block motion estimation represents a CPU-intensive task. For this reason, many fast algorithms have been developed to improve searching and matching phases. A milestone within the lossless approach is partial distortion elimination (PDE/SpiralPDE) in which distortion is the difference between the block to be coded and the candidate prediction block. In this paper, (i) we analyze distortion behavior from local information using the Taylor series expansion and show that our general analysis includes other previous similar approaches. (ii) Then, we propose two full-search (lossless), fast-matching, block motion estimation algorithms, based on the PDE idea. The proposed algorithms, called fast full search with sorting by distortion (FFSSD) and fast full search with sorting by gradient (FFSSG), sort the contributions to distortion and the gradient values, respectively, in order to quickly discard invalid blocks. Experimental results show that the proposed algorithms outperform other existing full search algorithms, reducing by up to 20% the total CPU encoding time (with respect to SpiralPDE), while the computation strictly required by the motion estimation is reduced by about 30%. (iii) Finally, we experimentally find an operational lower bound (based on standard test sequences) for the average number of checked pixels in the PDE approach, which measures the performance of the searching and matching phases. In particular, SpiralPDE achieves performances very close to the searching phase bound, while there is still a remarkable margin on the matching phase. We then show that our algorithms, aimed at improving the performances of the matching phase, achieve interesting results, significantly approaching this margin.

Improved multilevel successive elimination algorithm using efficient decision conditions

The computational process of the sum of the absolute difference (SAD) and the multilevel successive elimination algorithm (MSEA) are theoretically analyzed, and a new improved MSEA is proposed. The proposed algorithm reduces the computations required for judging invalid candidate blocks. The simulation results show that the proposed algorithm achieves a computational time savings of about 30 to 40% without additional hardware, compared to the MSEA.

Two techniques for improving performance on bus-based multiprocessors

In this paper, we explore two techniques for reducing memory latency in bus-based multiprocessors. The first one, designed for sector caches, is a snoopy cache coherence protocol that uses a large transfer block to take advantage of spatial locality, while using a small coherence block (called a subblock) to avoid false sharing. The second technique is read snarfing (or read broadcasting), in which all caches can acquire data transmitted in response to a read request to update invalid blocks in their own cache. We evaluated the two techniques by simulating 6 applications that exhibit a variety of reference patterns. We compared the performance of the new protocol against that of the Illinois protocol with both small and large block sizes and found that it was effective in reducing memory latency and providing more consistent, good results than the Illinois protocol with a given line size. Read snarfing also improved performance mostly for protocols that use large line sizes.