Intrinsic Gate Delay Time Research Articles

Modeling of a vertical tunneling transistor based on Gr-hBN- χ 3 borophene heterostructure

We present a computational study on the electrical behavior of the field-effect transistor based on vertical graphene-hBN-χ3 borophene heterostructure and vertical graphene nanoribbon-hBN-χ3 borophene nanoribbon heterostructure. We use nonequilibrium the Green function formalism along with an atomistic tight-binding (TB) model. The TB parameters are calculated by fitting tight-binding band structure and first-principle results. Also, electrical characteristics of the device, such as ION/IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. We show that the increase of the hBN layer number decreases subthreshold swing and degrades the intrinsic gate-delay time. The device allows current modulation 177 at room temperature for a 1.2 V gate-source bias voltage.

Analysis and simulation of asymmetrical nanoscale self-switching transistor

ABSTRACT In this paper, we present a computational study on the electrical behaviour of self-switching transistors (SSTs) based on InGaAs/InP heterojunction. Our simulation is based on the solution of Poisson and Schrodinger equations self-consistently by using Finite Element Method (FEM). By using this method, electrical characteristics of device, such as ratio, subthreshold swing, and intrinsic gate-delay time are investigated. Also, the effects of geometrical variations on the electrical parameters of SSTs are simulated. We show that appropriate design of the device allows current modulation exceeding at room temperature.

A comparative computational study of tunneling transistors based on vertical graphene–hBCN heterostructures

In this paper, the electrical characteristics of tunneling transistors based on vertical graphene and a hexagonal boron-carbon-nitrogen (hBCN) heterostructure are studied and compared theoretically. We have considered three different types of hBCN, i.e., BC2N, BC2N′, and BC6N as a tunneling barrier. Our simulation is based on the nonequilibrium Green’s function formalism along with an atomistic tight-binding (TB) model. The TB parameters are obtained by fitting the band structure to first-principles results. By using this method, electrical characteristics of the device, such as the ION/IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. For a fair comparison, the effects of geometrical variations and number of tunneling barrier layers on the electrical parameters of the device are simulated and investigated. We show that, by an appropriate design, the device can be used for low-power or high-performance applications. The device allows current modulation exceeding 106 at room temperature for a 0.6 V bias voltage.

Modeling of a Vertical Tunneling Transistor Based on Graphene–MoS2Heterostructure

In this paper, for the first time, we present a computational study on the electrical behavior of the field-effect tunneling transistor based on vertical graphene–MoS2 heterostructure and vertical graphene nanoribbon–MoS2 heterostructure. Our simulation is based on nonequilibrium Green’s function formalism along with an atomistic tight-binding (TB) model. The TB parameters are obtained by fitting the bandstructure to first-principle results. By using this model, electrical characteristics of device, such as ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. We show that the combination of tunneling and thermionic transport allows modulation of current by four orders of magnitude confirming experimental results. The results indicate that the increase of MoS2 layer numbers leads to a higher ${I}_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio but degrades the intrinsic gate-delay time. Furthermore, it can be observed from the results that as the ribbon width increases the ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of device increases at the cost of a lower ${I}_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio.

A computational study of vertical tunneling transistors based on graphene-WS2 heterostructure

In this paper, for the first time, we present a computational study on electrical characteristics of field effect tunneling transistors based on a vertical graphene-WS2 heterostructure and vertical graphene nanoribbon (GNR)-WS2 heterostructure (VTGNRFET). Our model uses the nonequilibrium Green's function formalism along with an atomistic tight binding (TB) method. The TB parameters are extracted by fitting the bandstructure to first principles results. We show that, due to the advantage of switching between tunneling and thermionic transport regimes, an improvement can be achieved in the electrical characteristics of the device. We find that the increase of the number of WS2 layers enhances the on/off conductance ratio but degrades the intrinsic gate-delay time. The results indicate that the on/off conductance ratio of VTGNRFET increases with decreasing the GNR width.

Scaling Effects on Static Metrics and Switching Attributes of Graphene Nanoribbon FET for Emerging Technology

In this paper, we have investigated the static metrics and switching attributes of graphene nanoribbon field-effect transistors (GNR FETs) for scaling the channel length from 15 nm down to 2.5 nm and GNR width by approaching the ultimate vertical scaling of oxide thickness. We have simulated the double-gate GNR FET by solving a numerical quantum transport model based on selfconsistent solution of the 3D Poisson equation and 1D Schrödinger equation within the non-equilibrium Green's function formulism. The narrow armchair GNR, e.g. (7,0), improved the device robustness to shortchannel effects, leading to better OFF-state performance considering OFF-current, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio, subthreshold swing, and drain-induced barrier-lowering. The wider armchair GNRs allow the scaling of channel length and supply voltage, resulting in better ON-state performance, such as the larger intrinsic cut-off frequency for the channel length below 7.5 nm at smaller gate voltage as well as smaller intrinsic gate-delay time with the constant slope for scaling the channel length and supply voltage. The wider armchair GNRs, e.g. (13,0), have smaller power-delay product for scaling the channel length and supply voltage, reaching to ~0.18 (fJ/μm).

An Inverter Gate Design Based on Nanoscale S-FED as a Function of Reservoir Thickness

In this paper, an inverter logic gate has been successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs). Effect of the reservoir thickness on the S-FED performance is investigated, and then the output characteristics of the S-FED-based inverter are studied and compared with those of the existing CMOS technology. The S-FED performance evaluation is performed in terms of important figures of merit for logic application in various reservoir thicknesses, including transconductance, intrinsic gate delay time, energy delay product, and subthreshold slope. The numerical results demonstrate that the optimum reservoir thickness is 7 nm, and the threshold voltage can be controlled by reservoir thickness. Mixed-mode simulations also indicate that, in the design of an inverter utilizing S-FEDs, the delay and the power dissipation of the logic gate are reduced. These results indicate that the S-FED can be an interesting candidate for designing low-power and high-speed logic gates.

Effects of the Spacer Length on the High-Frequency Nanoscale Field Effect Diode performance

The performance of nanoscale Field Effect Diodes as a function of the spacer length between two gates is investigated. Our numerical results show that the Ion/Ioff ratio which is a significant parameter in digital application can be varied from 101 to 104 for S-FED as the spacer length between two gates increases whereas this ratio is approximately constant for M-FED. The high-frequency performance of FEDs is investigated and the cut-off frequency of the intrinsic transistor without parasitic capacitance is calculated. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic applications.

Gate capacitance modeling and width-dependent performance of graphene nanoribbon transistors

The width-dependent performance of armchair GNRs-FETs is investigated by developing a fully analytical gate capacitance model based on effective mass approximation and semiclassical ballistic transport. The model incorporates the effects of edge bond relaxation and third nearest neighbor interaction as well as thermal broadening. To calculate the performance metrics of GNR-FETs, analytical expressions are used for the charge density, quantum capacitance as well as drain current as functions of both gate and drain voltages. Intrinsic gate delay time, cutoff frequency and Ion/Ioff ratio are also calculated for different GNR widths. Numerical results for a double-gate AGNR-FET operating close to quantum capacitance limit show that nanoribbon widths of about 3–4nm at most are required in order to obtain optimum on/off performance.

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

This work estimates electrical and transfer-characteristic fluctuations in 16-nm-gate high-κ/metal gate (HKMG) metal–oxide–semiconductor field effect transistor (MOSFET) devices and inverter circuit induced by random interface traps (ITs) at high-κ/silicon interface. Randomly generated devices with two-dimensional (2D) ITs at HfO2/Si interface are incorporated into quantum-mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to random ITs near source and drain ends. Owing to a decreasing penetration of electric field from drain to source, the drain induced barrier lowering (DIBL) of the edvice decreases when the number of ITs increases. In contrast to random-dopant fluctuation, the screening effect of device's inversion layer cannot effectively screen potential's variation; thus, devices still have noticeable fluctuation of gate capacitance (CG) under high gate bias. The cutoff frequency decreases as increasing the number of ITs owing to the decreasing transconductance and increasing CG. Decreasing on-state current and increasing CG further result in increasing intrinsic gate delay time (τ) when the number of ITs increases. The fluctuation magnitude of DIBL, cutoff frequency, and τ above is increased as the number of ITs increases. Even for cases with the same number of random ITs, noise margins (NMs) of the 16-nm-gate complementary metal–oxide–semiconductor inverter circuit are still quite different due to the different distribution of random ITs. The NMs of inverter circuit increase as the number of random ITs increases; however, the NMs' fluctuations are increased due to the more sources of fluctuation at HfO2/Si interface of HKMG devices.

Geometrical study of nanoscale field effect diodes

In this paper, the previously proposed side-contacted field effect diode (FED) is carefully studied and its characteristic is compared against that of a modified FED and a metal oxide semiconductor field effect transistor (MOSFET). The influences of the body thickness, each gate length and access resistance are investigated. The figures of merit including intrinsic gate delay time and energy-delay product, which represent the speed and switching energy of the device, respectively, are studied. Our results highlight that FEDs are good candidates for obtaining a high Ion/Ioff ratio with a relatively short delay time compared to conventional FEDs and MOSFETs. We show that by a careful scaling of the source–drain region, the access resistance can be optimized. We demonstrate that a well-tempered device with a high switching response and a lower energy consumption can be achieved with a 30 nm body thickness, 85 nm source–drain length and a drain gate length longer than the source gate length.

Performance Assessment of Nanoscale Field-Effect Diodes

We propose a new structure called a side-contacted field-effect diode (FED). The fabrication of this new structure is simple, and it offers good electrical characteristics. Furthermore, a comprehensive analysis of FEDs is presented. The effect of heavy-doping-induced band-gap narrowing on the performance of FEDs is investigated. Our results show that the calculated <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio is at least two orders of magnitude larger than that obtained from models neglecting this effect. The figures of merit including intrinsic gate delay time, the energy-delay product, and the subthreshold slope have been studied. Our numerical investigations of the scaling of FEDs indicate that, in the nanometer regime, FEDs have a higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio. The results demonstrate that FEDs are interesting candidates for future logic applications.