Intrinsic Body Diode Research Articles

Evaluation of antiparallel SiC Schottky diode in SiC MOSFET phase-leg configuration of synchronous rectifier

The MOSFET synchronous rectification (SR) is widely used to reduce the conduction loss during the freewheeling period. Due to the wide band gap of silicon carbide (SiC), the intrinsic body diode of SiC MOSFET exhibits a high voltage drop. Therefore, SiC Schottky diodes (SBD) and SiC MOSFETs are usually used in reverse parallel to reduce power loss. However, the increase of equivalent junction capacitance due to the addition of an external SiC SBD could bring larger turn-on current on opposite power transistor of the phase-leg. Furthermore, as the parasitic inductance associated with layout hinders the prompt transfer of current between SiC SBD and body diode, the external SiC SBD cannot be fully utilized, and it may deteriorate the overall performance, especially at heavy load. We comprehensively compare power losses when SiC SBD are antiparallel or not, at different working conditions, including different layout compactness, load current and dead time. It’s hard to get the effect of loss reduction loss when add antiparallel SiC SBD due to the parasitic inductance induced by the layout. The results can provide a guidance to properly select SiC SBD in a phase-leg configuration under SR mode for freewheeling during the dead time.

A SiC Planar MOSFET with an Embedded MOS-Channel Diode to Improve Reverse Conduction and Switching.

A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow through it. Therefore, the suggested device not only has a low diode cut-in voltage but also entirely suppresses the intrinsic body diode, which will cause bipolar deterioration. In order to clarify the barrier-lowering effect of the MOS-channel diode, an analytical model is proposed. The calibrated simulation results demonstrate that the diode cut-in voltage of the proposed device is decreased from the conventional voltage of 2.7 V to 1.2 V. In addition, due to the split-gate structure, the gate-to-drain charge (QGD) of the proposed device is 20 nC/cm2, and the reverse-transfer capacitance (CGD) is 14 pF/cm2, which are lower than the QGD of 230 nC/cm2 and the CGD of 105 pF/cm2 for the conventional one. Therefore, a better high-frequency figure-of-merit and lower switching loss are obtained.

Measurement and Analysis of Body Diode Stress of 3.3 kV Sic-Mosfets with Intrinsic Body Diode and Embedded SBD

SiC MOSFETs display reliability issues related to the quality of SiO2/SiC interface and bulk material due to the presence of near interface traps and point and extended material defects [1]. These material related issues give rise to a degradation of device reliability and ruggedness. One of them are basal plane dislocations (BPDs) introduced in the drift-layer during the epitaxial growth process which causes a s.c. bipolar degradation. Growth and movement of BPDs fueled by recombination energy has a very significant impact on conduction loss and on-resistance degradation. For 3.3 kV voltage capability, the probability of the appearance of BPDs is greater because the drift region is about three times larger compared to 1.2 kV devices [2-3]. We present measurement results and analysis of bipolar degradation in 3.3 kV MOSFETs with conventional body diode and embedded schottky barrier diode (SBD). The measurements were performed applying 50 % and 80 % of rated current with duty cycle 80 %, under total time of 100 hrs at constant case temperature of 54 °C. The 3rd-quadrant performance of both types of MOSFETs in pre-stress conditions was characterized at 25 and 150 °C with different gate biases of -10 V, 0 V, and +17 V. To evaluate the bipolar degradation, the diode conduction characteristics were measured at 25 °C after different stressing times by diode conduction the MOSFET output characteristics were measured at 25 and 54 °C before and after stressing the intrinsic body diode and embedded SBD. No VSD shift was observed in diode conduction characteristics. The results indicate that the MOSFETs were fabricated on appropriate material with a sufficiently low number basal plane dislocation (BPD). The on-state resistance with VGS = +17 V was decreased by temperature due to increased JFET resistance rather than bipolar degradation. On the other hand, the on-state resistance with VGS = +11 V was impacted by the increased temperature and VTH instability.

A Study on the Performance of AlGaN/GaN HEMTs Regrown on Mg-Implanted GaN Layers With Low Channel Thickness

In this work, a comprehensive study on the performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) regrown on Mg-implanted layers is shown. A comparably sharp doping profile into regrown AlGaN/GaN-stacks was verified by secondary-ion mass spectrometry (SIMS) even at standard metal–organic chemical vapor deposition (MOCVD) temperatures above 1000 °C. Static and dynamic characterization by a full 100-mm wafer map exhibited neither an impact on the threshold voltage, transconductance nor on the saturation current even for channel thicknesses as low as 150 nm. Slight current collapse was observed at high OFF-state conditions with large recovery times above 5 s indicating rather slow traps from the nonconnected p-GaN. Within the leakage current, three different mechanisms were identified across the vertical epi-stack. While variable-range hopping (VRH) dominates below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {DS}}}$ </tex-math></inline-formula> = 35 V, the Pool–Frenkel emission (PFE) was identified for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {DS}}} &gt;35$ </tex-math></inline-formula> V. At high electric fields ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} &gt;$ </tex-math></inline-formula> 1 MV/cm), the devices revealed either a direct change from PFE to drain-induced barrier lowering (DIBL) or a change from PFE to space-charge-limited currents (SCLCs) to DIBL was observed. The device results demonstrate the feasibility of the demonstrated process for reproducible device fabrication on large-scale wafers with low channel thicknesses for future device developments of CAVETs, SJ-HEMTs, p-GaN back gates, and intrinsic body diodes.

A novel SiC power MOSFET with integrated polySi/SiC heterojunction freewheeling diode

The adoption of intrinsic body diode of SiC MOSFETs as freewheeling diode (FWD) always induces high conduction loss and reverse recovery loss, therefore it is highly desirable to integrate a low loss FWD in SiC MOSFET. In this paper, we propose a new concept of monolithically integrating a polySi/SiC heterojunction diode (HJD) in SiC planar MOSFET (HJDMOS) without sacrificing MOSFET cell density or increasing much processing complexity. The HJD is formed between the gate polysilicon and the SiC JFET region using the same polysilicon deposition, thus the MOSFET and FWD can share the JFET and drift region in a time-multiplexing way. The SiC HJDMOS not only inactivates the body diode by offering lower turn-on voltage but also shows excellent reverse recovery characteristics because the HJD behaves like a Schottky barrier diode. Meanwhile, the gate-to-drain charge (Q gd) and gate-to-drain capacitance (C gd) of the SiC HJDMOS are significantly reduced by 8.0 times and 4.6 times in comparison with the conventional MOSFET due to the reduction of the overlapping area of gate and drain region. With optimal selection of design parameters, the integrated device maintains good MOSFET performances with forward blocking voltage of >1200 V and specific on-resistance (R on,sp) of 2.2 mΩ cm2. Therefore, the obtained figure-of-merits ( and ) of SiC HJDMOS are improved by around 7.5 times and 4.3 times, respectively. The enhanced performances suggest that SiC HJDMOS is an excellent choice for high efficiency and high frequency power electronic applications.

A non-invasive SiC MOSFET Junction temperature estimation method based on the transient light Emission from the intrinsic body diode

A non-invasive temperature sensing method for high-voltage SiC MOSFET chips based on the measurement of light emission during reverse conduction is proposed. The method is based on a compact sensing circuit that can be easily embedded in the package, allowing online temperature estimation. The effectiveness of the circuit has been confirmed by the analysis of a commercial SiC power module. The proposed temperature sensing strategy is fast, inexpensive, accurate, and non-invasive.

Investigation into the Body Diode Degradation of 6.5 kV SiC MOSFETs

The aim of this study is to investigate the main contributing factors to the degradation of the intrinsic body diode in SiC MOSFETs, caused by the expansion of stacking faults (SFs) from the substrate into the epitaxial layer, and how it affects their performance. Additionally, a comparison between DC forward current stress and surge current pulse stress is shown.

SiC-Based High Efficiency High Isolation Dual Active Bridge Converter for a Power Electronic Transformer

This paper discusses the benefits of using silicon carbide (SiC) devices in a three-stage modular power electronic transformer. According to the requirements to be fulfilled by each stage, the second one (the DC/DC isolation converter) presents the most estimable improvements to be gained from the use of SiC devices. Therefore, this paper is focused on this second stage, implemented with a SiC-based dual active bridge. Selection of the SiC devices is detailed tackling the efficiency improvement which can be obtained when they are co-packed with SiC antiparallel Schottky diodes in addition to their intrinsic body diode. This efficiency improvement is dependent on the dual active bridge operation point. Hence, a simple device loss model is presented to assess the efficiency improvement and understand the reasons for this dependence. Experimental results from a 5-kW Dual Active Bridge prototype have been obtained to validate the model. The dual active bridge converter is also tested as part of the full PET module operating at rated power.

Investigation on Degradation of SiC MOSFET Under Surge Current Stress of Body Diode

Eliminating antiparallel silicon carbide Schottky barrier diode (SiC SBD) and making use of the intrinsic body diode of SiC metal–oxide–semiconductor-field-effect transistor (SiC MOSFET) offer a cost-effectiveness solution without obviously sacrificing the conversion efficiency in some power converter applications. Although the body diode of commercial SiC MOSFET has been qualified by several manufacturers, the reliability of SiC MOSFET under repetitive surge current stress of body diode has not been sufficiently studied. In this article, the new degradation phenomena of SiC MOSFET’s gate oxide are observed, and the degradation mechanism is discussed when the intrinsic body diode of the 1200-V SiC planar gate MOSFETs was subjected to surge current stress. TCAD simulation and experimental measurements indicate that the generation and accumulation of electrons or holes within the gate oxide under surge current stress are the main reasons for the degradation of SiC MOSFET. Finally, a mitigation technique with optimal gate turn-off voltage is suggested to suppress the gate oxide degradation of the SiC MOSFET under surge current stress of its body diode.

Silicon carbide split-trench-source VDMOSFET with integrated Schottky barrier diode and reduced cell pitch

A new silicon carbide (SiC) VDMOSFET with an integrated split trench Schottky barrier diode (SBD) between split sources is proposed, namely STS-VDMOSFET, and investigated by 2D simulation. Compared with the SiC VDMOSFET integrated with SBD between split sources (SS-VDMOSFET), the cell pitch of the proposed structure can be greatly reduced apart from suppressing the conduction of the intrinsic body diode. Consequently, the active area of the proposed structure is 23% lower than that of the SS-VDMOSFET with the same on-state resistance, leading to reducing the cost effectively and the switching loss lightly. In addition, the trench-source can be etched during alignment mask without lithographic process of P+ implantation. In a word, the proposed structure is a superior choice for the SBD integration scheme solution because of the simplified process, excellent performance of device and the reduced cost.

Comparison of SiC Voltage Source Inverters Using Synchronous Rectification and Freewheeling Diode

For power converters with inductive loads, a freewheeling path is needed for the current due to reactive power. The MOSFET synchronous rectification (SR) is widely used to reduce the conduction loss during the freewheeling period. Due to the wide band gap of silicon carbide (SiC), the intrinsic body diode of SiC MOSFET exhibits a high voltage drop. Hence, an antiparallel SiC Schottky diode is normally implemented to eliminate its conduction. However, the external SiC Schottky diode is not fully utilized as it only works during the dead time. In this paper, the hard-switching SR is investigated in an SiC three-phase inverter and compared with a conventional inverter using freewheeling diode (FWD). An improved power loss model for the two inverters has been developed. It is found that the inverter using SR has higher efficiency due to the smaller switching loss. A 7-kW prototype of SiC three-phase inverter is built, which achieves a peak efficiency of 98.8% ( $\pm$ 0.15%) and 98.5% ( $\pm$ 0.15%) at 40 kHz using SR and FWD, respectively. This paper confirms that the SiC MOSFET is an ideal candidate for the SR.

Critical transient processes of enhancement-mode GaN HEMTs in high-efficiency and high-reliability applications

Wide-bandgap devices, such as silicon-carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) and gallium-nitride high electron mobility transistors (HEMTs), exhibit an excellent figure of merits compared to conventional silicon devices. Challenges of applying such fast switches include accurate extraction and optimization of parasitics especially when 6high-efficiency operation, all of which require the comprehensive understanding of such switch especially its interaction with peripheral circuits. Particularly for the enhancement-mode GaN HEMTs without the intrinsic body diode, when reverse conducting, its high voltage drop causes a high dead-time loss, which has rarely a concern in silicon devices. This paper focuses on 650V/30~60A enhancement-mode GaN HEMTs provided by GaN Systems, analytically models its switching behaviors, summarizes the impact of parasitics and dead time, and applies it in two DC/DC converters. Systematic design rules are generated not only for soft switching but also for hard switching applications.

Impact of Channel Mobility Improvement Using Boron Diffusion on Different Power MOSFETs Voltage Classes

SiC planar VDMOS of three voltages ratings (1.7kV, 3.3kV and 4.5kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO2/SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

Body diode reliability investigation of SiC power MOSFETs

A special feature of vertical power MOSFETs, in general, is the inbuilt body diode which could eliminate the need of having to use additional anti-parallel diodes for current freewheeling in industrial inverter applications: this, clearly, subject to their demonstration of an acceptable level of reliability. Recent improvements in Silicon Carbide (SiC) power MOSFET device manufacturing technology has resulted in their wider commercial availability with different voltage and current ratings and from various manufacturers. Hence, it is essential to perform characterisation of its intrinsic body diode. This paper presents the reliability assessment of body diodes of latest generation discrete SiC power MOSFETs within a 3-phase 2-level DC-to-AC inverter representing realistic operating conditions for power electronic applications.

Reducing Switching Losses in BLDC Motor Drives by Reducing Body Diode Conduction of MOSFETs

This paper presents a new power electronic topology that aims to reduce switching losses in hard-switched inverters for brushless dc (BLDC) motor drives. This is achieved by extending the benefits of synchronous rectification used in low-voltage switch-mode dc-dc conversion to high-voltage motor drive applications and by minimizing the reverse conduction behavior of the intrinsic body diode of the synchronous rectifier MOSFET. The proposed topology for reducing body diode conduction includes the addition of a MOSFET in series with the rectifying switch and a SiC Schottky diode around the series switch combination. This paper focuses on theory, simulations, and experimental results and validates the benefits of proposed new topology for BLDC motor drive applications. An extension of this topology for sinusoidal back electromotive force permanent-magnet motors is also presented.

Soft-Switching Bidirectional DC-DC Converter Using a Lossless Active Snubber

A soft-switching bidirectional dc-dc converter using a lossless active snubber is proposed in this paper. In the proposed converter, zero-voltage-switching (ZVS) of main switches is achieved by utilizing an active snubber which consists of auxiliary switches, diodes, an inductor, and a capacitor. Although conduction losses associated with additional components increase, switching losses are significantly reduced due to the ZVS operation of main switches. Therefore, total efficiency is improved. Moreover, there is no reverse-recovery problem of the intrinsic body diodes of the switches. To verify the ZVS of the main switches and efficiency improvement of the proposed bidirectional dc-dc converter, theoretical analysis and experimental results from a 200 W prototype are discussed.

Novel High-Efficiency Three-Level Stacked-Neutral-Point-Clamped Grid-Tied Inverter

In recent years, high photovoltaic array voltage up to 1000 V and transformerless grid-tied inverter have been increasingly researched and applied to elevate the inverter and the dc power collection efficiency. With the same reasons, a three-level neutral point clamped (3L-NPC) inverter featuring low power device voltage stress and low leakage current becomes increasingly attractive. In this paper, the operation and the features of a novel grid-tied 3L-NPC are presented. The proposed topology is a derivative of the three-level stacked neutral point clamped (3L-SNPC) structure. However, compared with the conventional 3L-SNPC and its pulse width modulation (PWM) strategy, the new topology with novel PWM strategy features completely inactive intrinsic body diodes. Furthermore, only two outer power devices are working with switching frequency, while the other four Insulated Gate Bipolar Transistors (IGBTs) are actually with the grid frequency. Therefore, the relatively high switching frequency is selected to reduce the inverter output filter inductance. A hybrid CoolMosfet and IGBT power module configuration is also proposed based on the new PWM strategy. The calculation shows that the total power device losses are reduced. The experimental results are illustrated in this paper to confirm the operation of the proposed topology and controller.