Intra-chip Interconnects Research Articles

IBM's POWER10 Processor

The IBM POWER10 processor represents the 10th generation of the POWER family of enterprise computing engines. It is built on a balance of computation and bandwidth, delivered by powerful processing cores and intrachip interconnect, respectively. Multiple system interconnect infrastructures support configurations with up to 16 processor chips and up to 1920 simultaneous threads of execution, as well as an expansive memory system with up to 2 Petabytes of addressing space. Cross-system memory sharing and coherent accelerator attach are also supported. The POWER10 processing core has been significantly enhanced over its POWER9 predecessor, including the addition of an all-new matrix math engine. Throughput gains from POWER9 to POWER10 average 30% at the core level and three-fold at the socket level. Those gains can reach ten- or twenty-fold at the socket level for matrix-intensive computations.

Globally Asynchronous, Locally Synchronous Clocking and Shared Interconnect for Large-Scale SFQ Systems

A globally asynchronous, locally synchronous clocking scheme for large-scale single flux quantum (SFQ) systems is proposed. In this scheme, the width of each data bus is extended to carry the corresponding clock signal. This signal activates the distribution of the clock signals within the receiving block. Based on this approach for intra-chip interconnect within SFQ systems, a configurable shared bus is also proposed. The data are attached to a tag, and a resulting data packet is sent to the shared bus. This packet is received by each block, but only processed if the tag matches the block identifier. By avoiding expensive comparators and multiplexers, the overhead of the global bus connection is reduced. The proposed approaches exploit the pulse-based nature and ambiguity of clock and data in SFQ technology – the data packet propagating through the interconnect carries a local clock signal.

Expansible Network-on-Chip Architecture

Interconnection has a great importance to provide a high bandwidth communication among parallel systems. On multi-core context, Network-on-Chip is the default intra-chip interconnect ...

Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications

We propose a novel antenna design enabled by 3-D printing technology for future wireless intrachip interconnects aiming at applications of multicore architectures and system-on-chips. In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially designed dielectric property distribution. This additional degree of freedom in design enabled by 3-D printing technology is used to tailor the electromagnetic wave propagation. As a result, the desired wireless link gain is enhanced and the undesired spatial crosstalk is reduced. Simulation results show that the proposed dielectric loading approach improves the desired link gain by 8-15 dB and reduces the crosstalk by 9-23 dB from 155 to 165 GHz. As a proof-of-concept, a 60 GHz prototype is designed, fabricated, and characterized. Our measurement results match the simulation results and demonstrate 10-18 dB improvement of the desired link gain and 10-30 dB reduction in the crosstalk from 55 to 61 GHz. The demonstrated transmission loss of the desired link at a distance of 17 mm is only 15 dB, which is over 10 dB better than the previously reported work.

Nonlinear Properties of Ge-rich Si1\u2212xGex Materials with Different Ge Concentrations

Silicon photonics is a large volume and large scale integration platform for applications from long-haul optical telecommunications to intra-chip interconnects. Extension to the mid-IR wavelength range is now largely investigated, mainly driven by absorption spectroscopy applications. Germanium (Ge) is particularly compelling as it has a broad transparency window up to 15 µm and a much higher third-order nonlinear coefficient than silicon which is very promising for the demonstration of efficient non-linear optics based active devices. Si1−xGex alloys have been recently studied due to their ability to fine-tune the bandgap and refractive index. The material nonlinearities are very sensitive to any modification of the energy bands, so Si1−xGex alloys are particularly interesting for nonlinear device engineering. We report on the first third order nonlinear experimental characterization of Ge-rich Si1−xGex waveguides, with Ge concentrations x ranging from 0.7 to 0.9. The characterization performed at 1580 nm is compared with theoretical models and a discussion about the prediction of the nonlinear properties in the mid-IR is introduced. These results will provide helpful insights to assist the design of nonlinear integrated optical based devices in both the near- and mid-IR wavelength ranges.

Enabling inter- and intra-chip optical wireless interconnect by the aid of hybrid plasmonic leaky-wave optical antennas

In this paper, we propose a new method to provide optical link in Photonic Integrated Circuits (PICs). The proposed method uses two hybrid plasmonic leaky-wave optical antennas, operating at the standard optical telecommunication wavelength of 1.55μm, to provide inter-chip interconnect between two layers in a photonic chip and also intra-chip interconnect between two different photonic ICs. Linearly tapered couplers are designed to couple the optical signal from the silicon waveguide to the hybrid plasmonic antennas. The performance of the proposed optical link is verified using numerical full wave simulation. The proposed structure is planar, and can be fabricated using standard CMOS technology which makes it the superior candidate for realization of future multi-layered Photonic Integrated Circuits.

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks

Recently, interchip/intrachip optical interconnection networks have been proposed for ultrahigh-bandwidth and low-latency communications. These networks employ the microresonators (MRs) to modulate, direct, or detect the optical signal. However, utilized MRs suffer from intrinsic crosstalk noise and signal power loss, degrading the network efficiency via the signal-to-noise ratio (SNR). The amount of crosstalk noise and signal power loss may differ from network to network. Hence, there exists a need to systematically analyze the effect of the crosstalk noise and the power loss issues. In this paper, we have developed the analytical models considering both coherent and incoherent crosstalk for both the interchip and intrachip optical networks. The interchip/intrachip optical interconnection networks—the $\text{I}^{2}$ CON—are analyzed as a case study. The quantitative results on the individual networks have demonstrated that the architectural design determines the impact of crosstalk on the SNR. We have also demonstrated that the optical interconnection networks with interchip/intrachip interconnects result in better bit error rate (BER) compared with that of only intrachip interconnect. Our analyses of the worst case can be utilized as a platform to compare the realistic performance among different optical interconnection networks via the degradation of SNR/BER and data bandwidth.

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks

As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. The Helix-h non-blocking photonic switch is developed to improve physical-layer and network performance parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Traffic benchmarks and practical case studies using a cycle-accurate simulation environment indicate significantly reduced insertion loss providing improved bandwidth density and scalability to manycore plurality. Improvements in system performance parameters are quantified for network bandwidth, transmission efficiency, and latency in popular photonic internconnection topologies, in comparison to previous switch designs. For instance, utilizing the Helix-h switch in a mesh topology, the bandwidth is increased by 112 percent compared to the previously highest performing switch design. Execution time and energy efficiency are improved by up to 92 and 99 percent, respectively, for representative multicore applications. Finally, the technique is generalized to a novel graph-theoretic method for articulating blocking conditions in photonic switches.

Bufferless Routing in Optical Gaussian Macrochip Interconnect

The ever increasing intra-chip and inter-chip traffic load in computing systems has been pushing traditional electronic interconnects to their limit in communication bandwidth, latency, and energy consumption. In order to achieve the high bandwidth and low latency required by intra-chip and inter-chip communications and mitigate the high interconnect power dissipation, optical interconnects have been considered as a promising candidate for intra-chip and inter-chip interconnections in next generation computing systems. In addition, packet switching is an efficient switching paradigm to fully utilize the communication bandwidth. However, due to lack of random access optical memory, it is challenging to implement all-optical packet switching in optical interconnects. In this paper, we exploit bufferless routing, a special type of packet-switching, to overcome the problem of lack of random access optical buffer. More specifically, we study bufferless routing in a novel optical multichip system, called Gaussian macrochip, where embedded chips are interconnected by an optical Gaussian network. By taking advantage of the underlying Hamiltonian cycles in the Gaussian network, we design a bufferless routing algorithm for the Gaussian macrochip, which routes packets along the shortest path in the absence of deflection, and guarantees that deflected packets reach their destinations within ${{N}}$ hops. Our extensive simulation results demonstrate that by adopting the proposed routing algorithm, Gaussian macrochip can support much higher inter-chip communication bandwidth, has much shorter average packet delay, and is more power efficient than the previously proposed architectures for optical multichip systems.

Silicon photonic devices and integrated circuits

AbstractSilicon photonic devices and integrated circuits have undergone rapid and significant progresses during the last decade, transitioning from research topics in universities to product development in corporations. Silicon photonics is anticipated to be a disruptive optical technology for data communications, with applications such as intra-chip interconnects, short-reach communications in datacenters and supercomputers, and long-haul optical transmissions. Bell Labs, as the research organization of Alcatel-Lucent, a network system vendor, has an optimal position to identify the full potential of silicon photonics both in the applications and in its technical merits. Additionally it has demonstrated novel and improved high-performance optical devices, and implemented multi-function photonic integrated circuits to fulfill various communication applications. In this paper, we review our silicon photonic programs and main achievements during recent years. For devices, we review high-performance single-drive push-pull silicon Mach-Zehnder modulators, hybrid silicon/III-V lasers and silicon nitride-assisted polarization rotators. For photonic circuits, we review silicon/silicon nitride integration platforms to implement wavelength-division multiplexing receivers and transmitters. In addition, we show silicon photonic circuits are well suited for dual-polarization optical coherent transmitters and receivers, geared for advanced modulation formats. We also discuss various applications in the field of communication which may benefit from implementation in silicon photonics.

Low Latency and Energy Efficient Optical Network-on-Chip Using Wavelength Assignment

Optical network-on-chip (ONoC) is a promising technology for high-performance and energy-efficient intra-chip interconnection. Many existing proposals resort to high-density wavelength division multiplexing (WDM) to increase bandwidth and to mitigate contention. Unfortunately, high-density WDM increases the cost of optical devices and the difficulties of integration. We propose WANoC, a novel ONoC design with careful wavelength assignment aimed at more effective reuse. A novel WDM optical router is also designed with simple layout, which needs fewer waveguides and has fewer crossings. The simulation results show that the saturation load is improved more than 2.7 times, while the energy consumption is decreased by 33% compared with prior circuit-switched ONoC.

Model Pulses for Performance Prediction of Digital Microelectronic Systems

Pulse-shape models are presented that furnish the tools for analyzing a number of aspects of the performance of microelectronic circuits. Model pulse shapes are provided and their properties are analyzed in detail. Applications that are covered include the replication of measured pulses that are of relevance for inter- and intra-chip interconnects and, concurrently, examples of passive circuits that generate them. The pulses are appropriate as input to time-domain electromagnetic simulation. They are also instrumental to microelectronic performance prediction protocols and measurement equipment-aspects that are of crucial importance to integrated circuit packaging.

Characteristics of on-chip dipole antenna using diamond for intra-chip wireless interconnect

In this paper, a 2-mm long on-chip dipole antenna pair on silicon substrate is simulated to investigate the transmission characteristics. A novel technique is proposed by employing a 0.35-mm thick diamond layer between silicon substrate and heat sink to improve antenna performance. The simulated transmission gain of this antenna pair with 1 mm separation on a 10-Ω cm silicon substrate increases by 9 dB at 20 GHz. A modified plane wave model involving diamond layer is also presented to explain gain improvement. Effects of dielectric variety, diamond thickness, substrate resistivity and antenna pair separation on transmission gain have been studied. The results indicate that thinner diamond layer along with high resistivity substrate is preferred. Our method makes integrated dipole antennas well suitable for intra-chip wireless interconnection which is known as a future solution to replace critical wiring interconnection.

Ge-Photodetectors for Si-Based Optoelectronic Integration

High speed photodetectors are a key building block, which allow a large wavelength range of detection from 850 nm to telecommunication standards at optical fiber band passes of 1.3–1.55 μm. Such devices are key components in several applications such as local area networks, board to board, chip to chip and intrachip interconnects. Recent technological achievements in growth of high quality SiGe/Ge films on Si wafers have opened up the possibility of low cost Ge-based photodetectors for near infrared communication bands and high resolution spectral imaging with high quantum efficiencies. In this review article, the recent progress in the development and integration of Ge-photodetectors on Si-based photonics will be comprehensively reviewed, along with remaining technological issues to be overcome and future research trends.

Nanowire Photodetectors

The use of nanowires and nanowire structures as photodetectors is an emerging research topic. Despite the large amount of reports on nanowire photoresponse that appeared in the literature over the last decade, the mechanism leading to high photosensitivity and photoconductive gain in high aspect ratio nanostructures has been elucidated only recently. Novel device architectures integrated in single nanowire devices are also being actively studied and developed. In this article, the general nanowire photodetector concepts are reviewed, together with a detailed description of the physical phenomena occurring in nanowire photoconductors and phototransistors, with some examples from recent experimental results obtained in our groups. An outlook on future directions toward the use of semiconductor nanowire photoconductors as intrachip interconnects, single-photon detectors, and image sensors, is also given.

Plasmonic interconnects versus conventional interconnects: a comparison of latency, crosstalk and energy costs

The continued scaling of integrated circuits will require advances in intra-chip interconnect technology to minimize delay, density of energy dissipation and cross-talk. We present the first quantitative comparison between the performance of metal wire interconnects, operated in the traditional manner by electric charge and discharge, versus the performance of metal wires operated as surface plasmon waveguides. Surface plasmon wire waveguides have the potential to reduce signal delay, but the high confinement required for low cross-talk amongst high density plasmon wire interconnects significantly increases energy dissipation per transmitted bit, above and beyond that required for electric charge/discharge interconnects at the same density.

Intra-chip wireless interconnections based on high performances integrated antennas

The feasibility of wireless intra-chip interconnections is presented. Integrated antennas and transmitted electromagnetic waves properties are investigated via simulation and experimental results. Materials and metallization design impact on system performances is found critical. Their study leads to the definition of high-performance structures manufactured via standard dual damascene processes. As a result, excellent propagation characteristics are obtained with crosstalk effects between antenna and nearby lines of the same order with those of traditional interconnects, thus demonstrating the viability and economic interest of wireless interconnects.

Micrometre-scale silicon electro-optic modulator

Metal interconnections are expected to become the limiting factor for the performance of electronic systems as transistors continue to shrink in size. Replacing them by optical interconnections, at different levels ranging from rack-to-rack down to chip-to-chip and intra-chip interconnections, could provide the low power dissipation, low latencies and high bandwidths that are needed. The implementation of optical interconnections relies on the development of micro-optical devices that are integrated with the microelectronics on chips. Recent demonstrations of silicon low-loss waveguides, light emitters, amplifiers and lasers approach this goal, but a small silicon electro-optic modulator with a size small enough for chip-scale integration has not yet been demonstrated. Here we experimentally demonstrate a high-speed electro-optical modulator in compact silicon structures. The modulator is based on a resonant light-confining structure that enhances the sensitivity of light to small changes in refractive index of the silicon and also enables high-speed operation. The modulator is 12 micrometres in diameter, three orders of magnitude smaller than previously demonstrated. Electro-optic modulators are one of the most critical components in optoelectronic integration, and decreasing their size may enable novel chip architectures.

Reverse biased porous silicon light-emitting diodes for optical intra-chip interconnects

We have reported recent progress in development of the integrated optoelectronic unit on a Si chip. The developed optoelectronic unit includes a porous Si light-emitting diode (LED) connected with a photodetector by an alumina waveguide. Main attention has been devoted to the enhancement of LED parameters. Quantum efficiency as high as 0.4% has been reached. The delay time of 1.2 ns and the rise time of 1.5 ns have been measured for the diodes. Further improvements are also discussed.

Photophysical properties of nano Si/SiO x composites in Al/composite/mono Si structures for green light emitting and photodetector-Schottky diodes

The concept of the self-formation of a nanocrystallite (nc-) Si/SiO x : Si z O y Al nanocomposite at the Al/oxidized porous silicon interface in the result of solid-phase processes between Al and oxidized porous Si (PS) and the influence of its composition on photophysical properties were developed and experimentally confirmed for the Si chip with optical intra-chip interconnect consisting of light emitting and photodetector diodes and alumina waveguide on oxidized PS surface with aluminum electrodes. The peculiarities of nanocomposite photophysical properties (the refractive index, photoluminiscence (PL) peak situation, PL spectrum shape in the green range) have been shown to be due to the quantum confinement effects (revealed by XPS, Raman spectroscopy) and depend on the Al presence in the nanocomposite (obtained by XPS, IR spectroscopy). The experimental confirmation of this concept is (i) the shift of the nc-Si valence band relatively to that of monocrystalline Si (c-Si) on 0.2–0.7 eV for nc-Si size in 2.5–6.5 nm range; (ii) the decrease of Si nanocrystallite size in the Al presence; (iii) the approach of the value of the refractive index of nc-Si : SiO : Si 2O 3 : Si z O y Al nanocomposite at λ=236 nm to that of porous Si with 45% porosity and (iv) the stable green PL spectra in the Si z O y Al presence in the nanocomposite.