Interrupt Latency Research Articles

3GPP Edge–Fog federation: Transparent 3rd-party authentication and application mobility

3GPP edge and fog computing paradigms provide computational services to users at low latency. These paradigms alone are not enough to fulfill the users’ requirements completely. Therefore, a federation among these computing paradigms is necessary. To realize such federation, there is a need of an authentication mechanism where subscribers of a fog, can access 3GPP edge’s services, or vice versa, without buying new subscription, and an application mobility mechanism for continuous service during handover from 3GPP edge to fog, or vice versa, without re-authentication. In this work,33This work is an extension of [1] with inclusion of two new scenarios, extended testbed, and more results. we propose: (1) a proxy-based state transfer and third-party authentication (PS3A), that uses a transparent proxy to transfer the authentication and application state information between 3GPP edge and fog, and (2) a token-based state transfer and proxy-based third-party authentication (TSP3A), that uses the proxy to transfer the authentication information and tokens to transfer application state information between 3GPP edge and fog. The proxy plays different roles, via virtual counterparts of entities involved in these protocols, to provide transparency. When the 3GPP edge, using EPS-AKA, receives an authentication request, the proxy relays and behaves as a virtual Home Subscriber Server (vHSS) for the 3GPP edge, and behaves as a virtual user for the fog, which is using OIDC. We applied PS3A and TSP3A to three federation scenarios among 3GPP edge and fog. Experimental results show that PS3A and TSP3A provide authentication within 0.345–2.858 s for a 0–100 Mbps proxy load. The results further show that TSP3A provides application mobility, while taking 40%–52% less time than PS3A, using state tokens. TSP3A and PS3A also reduce the service interruption latency by 82.4% and 84.6%, compared to the cloud-based service, via tokens and prefetching.

Interrupt Latency Accurate Measurement in Multiprocessing Embedded Systems by Means of a Dedicated Circuit

Modern multiprocessing embedded applications require, in many cases, two different environments on the same platform: one that meets real-time requirements and another one with a general purpose operating system. Although several technologies can be used, two of the most popular are virtualization based on hypervisors and asymmetric multiprocessing software. However, using these tools introduces latency, which must be measured to verify compliance with real-time requirements. With the aim of facilitating these measurements, this work provides a hardware tool that is more precise and easier to use than other existing software solutions. The paper also studies the interrupt latency generated by different hypervisors and asymmetric multiprocessing frameworks in a Zynq UltraScale+ platform. This research work facilitates the accurate study of the temporal response of multiprocessor embedded systems, which allows for evaluating their suitability for applications with real-time requirements.

Interrupt Stack Protection for Linux Kernel in Hardware Virtualization Layer of ARM64 Architecture

Kernel security is of paramount importance in computer systems. As the number of vulnerabilities in the kernel continues to grow, computer systems security risks are increasing. To prevent the kernel interrupt stack from being attacked, researchers provide discussion over complete hypervisor supervision and kernel co-layer security domain techniques. Complete hypervisor supervision brings a heavy overhead and co-layer security domain techniques cannot achieve privilege-level isolation. We focus on memory-based security threats in kernel security vulnerabilities, protecting the kernel at a higher level by using virtualization technology. Compared with the existing work, our implementation method achieves a small performance loss to protect the interrupt stack. We have implemented our system on openEuler operating systems and Phytium processors. Although the deployment of protection code will result in increased kernel interrupt latency and processor overhead, experimental verification shows that the overall system overhead is acceptable.

A Measuring Tool for Interrupt Latency Based on Linux

Linux has been used more and more in the field of industrial control and robot control, the non-real-time nature of the final human-computer interaction program may cause system performance impact in industrial production. Interrupt response time is an important indicator to measure the real-time performance of real-time operating systems. Accurate test data can be used as an evaluation index for selecting the real-time performance of the operating system. In order to improve the real-time performance of Linux, analyze real-time problems, and solve possible real-time bottlenecks, this paper designs a probe-type tool that can measure the interrupt response time, output the interrupt call stack, and analyze the reasons for high interrupts. By optimizing specific limited and high-latency paths, Linux can still maintain an acceptable range of latency for a long time under various high-load scenarios. After testing, the tool has good measurement accuracy, which provides a basis for developing real-time tasks and solving real-time problems.

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

In dynamic real-time systems (RTS), the synchronous communication model is a source of unpredictable behaviors caused by the difficulty of estimating the maximum lockdown time in a process. Inter-task communication is a critical issue in RTS, even in the case of uniprocessor architectures. Using an FPGA-based development platform, through an SoC project, the implementation of HW_nMPRA_RTOS (a unified acronym for multi pipeline register architecture (nMPRA) where <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> is the degree of datapath resource multiplication, hardware scheduler engine (nHSE) for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> threads and RTOS application programming interface (API)), dedicated processor architecture was developed, simulated and validated. This paper propose an innovative soft-core implementation to reduce interrupt latencies, while maintaining strong spatial and temporal isolation. Among the results which contain relevance and novelty, we can mention: rapid tasks context switching (1 clock cycle); The implementation of a distributed and versatile interrupt system which allows the interrupt attachment to any task; The implementation of a static scheduler and support for the dynamic tasks scheduling; Rapid response to events of up to 2 clock cycles. We demonstrate the architecture’s predictability, scalability, and performance by running a set of benchmark applications on several configurations of HW_nMPRA_RTOS synthesized on a Xilinx 7 Series FPGA.

Distributed Information Exchange With Low Latency for Decision Making in Vehicular Fog Computing

Traditional decision making in a vehicle network includes uploading vehicle sensing data to faraway cloud platforms and then returning correlated results to the vehicles. The data have features of large quantity and high redundancy, which causes high communication latency and vehicle applications to deteriorate. Vehicular fog computing (VFC) is a new network paradigm that uses local fog nodes for decision making. However, how to achieve distributed information exchange with low latency is a challenging issue because the connectivity of the vehicle network is low due to vehicle mobility. In this article, a distributed information exchange scheme with low latency in VFC is proposed. First, considering the frequent changes in vehicle positions and the randomness in driving routes, public transportation facilities with a wider driving range such as buses and taxis are used as fog nodes to increase the probability of uploading data. Then, the fog nodes should dynamically adjust the data sampling frequency according to the time-space correlation of the data to ensure that only nonredundant data are received. To minimize the interruption latency caused by accidents during an exchange, the fog nodes evaluate and predict connection states among them and their neighboring vehicles when establishing exchanges. If a fog node finds that a vehicle cannot complete information exchange because the vehicle may move outside its communication range in a future period, it will recalculate an optimized relay route for the vehicle by using mixed integer programming. Theoretical analysis and simulation results show that compared with the existing work, the proposed scheme can completely exchange all vehicle data with lower latency.

Real-Time Performance Analysis and Tuning of Embedded System Virtualization Architecture Based on KVM

Embedded systems are proceeding towards exploiting virtualization technology to have the benefits of Real-Time Operating System (RTOS) and General-Purpose Operating System (GPOS) in the same system. This combination provides both a timely and deterministic behavior and a general-purpose application codebase. There still exist concerns about the real-time responsiveness of RTOS running inside a Virtual Machine (VM). In this paper, the real-time performance of Kernel-based Virtual Machine (KVM) virtualization architecture is analyzed on a multi-core system. Here, a preemptible Linux kernel with the PREEMPT_RT patch is used for RTOS, while a standard Linux kernel is used for GPOS. The interrupt latency inside the real-time guest VM is analyzed by applying various amounts of CPU, memory, and I/O stresses on the guest and host systems. A VM resource monitoring tool ‘VM_stat’ is developed to know the resource usage of the guest VMs, which is useful for effectively tuning the system. Different real-time tuning measures are applied on the host/guest systems and the performance is analyzed.

NemesisGuard: Mitigating interrupt latency side channel attacks with static binary rewriting

Internet of Things (IoT) is becoming integrated into nearly every aspect of our modern life. Indeed, exploitation of such devices can directly lead to physical consequences in the real world. Previous work has shown that IoT devices can be compromised by exploits in lower software layers such as the Operating System (OS). Embedded Trusted Execution Environments (TEEs) provide a small Trusted Computing Base (TCB) to protect sensitive codes and data in such devices. TEEs assume a strong threat model where even a privileged attacker (e.g. OS) cannot compromise the confidentiality and integrity of the execution. Nevertheless, it has been shown that side channel attacks make it challenging to keep secrets during application execution.Interrupt latency side channel attacks (a.k.a. Nemesis) are a novel type of timing attacks that target embedded TEEs and extract application secrets from them. Nemesis attacks exploit the CPU’s interrupt mechanism to reveal microarchitectural instruction timings from embedded TEEs. Specifically, the attacker measures the latency of a precisely timed interrupt to differentiate between secret-dependent branches. In this paper, we present NemesisGuard, the first mitigation mechanism against such side channel attacks that does not require a modified compiler or hardware and can protect COTS binaries without access to source code. NemesisGuard applies a novel static binary instrumentation technique to balance secret-dependent branches in IoT application binaries. Evaluation of NemesisGuard shows that it mitigates Nemesis side channel attacks effectively and efficiently.

An Empirical Study on System Level Aspects of Internet of Things (IoT)

Internet of Things (IoT) is an integration of the Sensor, Embedded, Computing, and Communication technologies. The purpose of the IoT is to provide seamless services to anything, anytime at any place. IoT technologies play a crucial role everywhere, which brings the fourth revolution of disruptive technologies after the internet and Information and Communication Technology (ICT). The Research & Development community has predicted that the impact of IoT will be more than the internet and ICT on society, which improves the well-being of society and industries. Addressing the predominant system-level design aspects like energy efficiency, robustness, scalability, interoperability, and security issues result in the use of a potential IoT system. This paper presents the current state of art of the functional pillars of IoT and its emerging applications to motivate academicians and researches to develop real-time, energy-efficient, scalable, reliable, and secure IoT applications. This paper summarizes the architecture of IoT, with the contemporary status of IoT architectures. Highlights of the IoT system-level issues to develop more advanced real-time IoT applications have been discussed. Millions of devices exchange information using different communication standards, and interoperability between them is a significant issue. This paper provides the current status of the communication standards and application layer protocols used in IoT with the detailed analysis. The computing paradigms like Cloud, Cloudlet, Fog, and Edge computing facilitate IoT with various services like data offloading, resource and device management, etc. In this paper, an exhaustive analysis of Edge Computing in IoT with different edge computing architectures and existing status are deliberated. The widespread adoption of IoT in society has resulted in privacy and security issues. This paper emphasizes on analyzing the security challenges, privacy and security threats, conventional mitigation techniques, and further scope for IoT security. The features like fewer memory footprints, scheduling, real-time task execution, fewer interrupt, and thread switching latency of Real-Time Operating Systems (RTOS) enables the development of time critical IoT applications. Also, this review offers the analysis of the RTOS’s suitable for IoT with the current status and networking stack. Finally, open research issues in IoT system development are discussed.

A Procedure For Avoid Overrun Error in Universal Synchronous Asynchronous Receiver Transmitter (Usart) by Utilizing Dummy Join and Interrupt Latency Method

In parallel interaction quantity of line between receiver and transmitter is dependent upon range bits to be sent, to transmit one byte 8 lines are needed b etween transmitter and receiver which raise the expense. Nevertheless as a result of overlapping between lines cross talk will take place, to conquer this blem that is professional interaction US ART is employed. US ART is a computer device that is competent to transform parallel to serial during the transmitter serial and end to parallel during the receiver age nd. Nonetheless US ART suffer from overrun mistake, parity mistake and mistake that is framing blem. In this paper author has professional t that is posed m ethods in other words dummy register and interrupt latency through which we can avoidoverrun mistake in United States ART

A hybrid approach to testing for nonfunctional faults in embedded systems using genetic algorithms

SummaryEmbedded systems are challenging to program correctly, because they use an interrupt‐driven programming paradigm and run in resource‐constrained environments. This leads to various classes of nonfunctional faults that can be detected only by customized verification techniques. These nonfunctional faults are specifically related to usage of resources such as time and memory. For example, the presence of interrupts can induce delays in interrupt servicing and in system execution time. Such delays can occur when multiple interrupt service routines and interrupts of different priorities compete for resources on a given CPU. As another example, stack overflows are caused when the combination of active methods and interrupt invocations on the stack grows too large, and these can lead to data loss and other significant device failures. To detect these types of nonfunctional faults, developers need to estimate worst‐case resource usage. Most existing approaches for calculating such estimates are based on static analysis; however, these have a tendency to overapproximate the resources needed. Dynamic techniques such as random testing, in contrast, often underapproximate resource usage. In this article, we present SimEspresso, a framework that uses a combination of static analysis and a test case generation algorithm to estimate worst‐case resource usage. There are three different worst‐case resource usage scenarios that we consider: (1) worst‐case execution times, (2) worst‐case interrupt latencies, and (3) worst‐case stack usage. SimEspresso first uses static analysis to identify program paths and interrupt interleavings that potentially lead to worst‐case scenarios. It then uses a genetic algorithm to generate test cases that guide program execution down these paths, using these particular interrupt interleavings. We performed an empirical study to evaluate the effectiveness of SimEspresso; our results show that SimEspresso is more effective than static analysis approaches and improves significantly over the state of the art dynamic technique, random test case generation. We also find that when we use only the genetic algorithm, omitting the static analysis, SimEspresso performs almost as effectively, but takes significantly longer to complete its task.

Hardware‐in‐the‐loop real‐time platform for more electric aircraft

Real-time test platform based on hardware-in-the-loop (HIL) simulation technology, troubleshooting for real-time problems such as interrupt latency and interface communication before physical testing, can effectively improve the traditional development process, shorten the research and development cycle, and reduce the cost and risk of test. Based on the technologies of virtual instrument, mathematical modelling, and HIL simulation, a real-time simulation framework combining the discrete-time converter system and the continuous-time motor system is proposed. Combined MATLAB/Simulink, dSPACE, and real-time hardware, an HIL real-time test platform is designed for the prototype and proper testing of the electrical control unit of more electric aircraft. The results and design principles of a three-stage brushless synchronous starter/generator system emulation using HIL simulation are presented.

Features of real-time systems

The purpose of the work is to analyze the features and functioning of the RTS, RT operating systems (RTOS) and the development of applied programs (AP) for RTS; RTS standards; characteristics and analysis of the RTOS; problems of extensions of RT based on Linux and Windows.The main differences between the RTOS and the general purpose OS are shown: the main task is to have time to react to events at the site; an RTOS is a tool for creating a specific SRT. The following characteristic functions of RTOS are distinguished: multitasking with preemption; realizing priorities for threads; predictable synchronization mechanisms; providing inheritance of priorities; behavior is known and predictable; for all scenarios of the STR the maximum response time is determined.It is shown that the processing of events in SRT depends on the field of application and hardware; events are reported via IRQ, so the key parameter is the response time of the interrupt latency. There is no generally accepted method for determining this parameter, but it can be predicted/ computed. The reaction time for an event is calculated by the value of its components, taking into account the worst situation for the SRT (the microprocessor is loaded, and actions that block interrupts). The evaluation of response times to the interruption of the RTOS is performed based on the data of the target SRT testing. Estimating the processing time for parallel events is determined by the context switching time.It was noted that the RTOSRTS is running on industrial computers in connection with which the RTOS should work in diskless execution, support, as much as possible, the microprocessor and types of special equipment, have tools for creating and debugging AP.The RTS standards (POSIX, DO-178A/ B/ C, ARINC-653, ED-12B, OSEK/ VDX (OSEK), SCEPTRE, TCSEC, etc.) are analyzed, their characteristics are given and it is shown that the importance of standards is that they are an axiomatic basis that defines the definitions of objects and concepts. It is shown that, from the point of view of the programmer, "Common Criteria ..." can be considered as a set of libraries which helps to write the tasks on security, typical security profiles, etc.Such properties of common RTOS are considered: POSIX compliance; rapidity and efficiency; they are modular and scalable; they support two-stage interrupt processing, have planning schemes, high resolution timers and counters; there are mechanisms for swapping and protecting memory; tasks and the kernel are executed in a single address space; correspond to Host-Target or SelfHosted.The analysis of the RTOS (CHORUS; LynxOS; OS-9; pSOS; RTC; VRTX; VxWorks; QNX, etc.) is presented in the format: name, main characteristics: type; architecture; standard; Properties as RTOS; operating system (host); processors (target); communication lines host-target; the minimum size; means of synchronization and interaction; development tools.The problems of adaptation to the requirements of the RT are considered. It is shown that the adaptation of Linux to the requirements of the RT is carried out in such directions: in accordance with the POSIX standard; the support of special hardware, running Linux from ROM, the resolution increase of the system timer; implementation of the preemption mechanism for the kernel. There are two ways to implement preemption for the Linux kernel: to rewrite the kernel, to implement the mechanism of preemption as a microcoder for scheduling interrupts and tasks.W’NT adaptation, based on the elements of the RT, was carried out in two ways: (1) the use of the conventional RTOS core as an addition to the core W’NT (the technology of using two OS on one computer); (2) PB integrating into W’NT by avoiding delays and hangs with the help of the RT extensions.The use of digital technologies in the aviation and space industry raises the need for training specialists, which in turn requires the availability of teaching aids, teaching staff and a technical training base. The experience of applying RTS in solving problems of automation of experimental research allows organizing the training of students in studying the principles of constructing and implementing components of the RTS.

Performance Based Improvement of the CPU by reducing the Real-Time Interrupt Latency using the PPTS Algorithm

The main objective of the research is to improve the performance of the CPU at software level by reducing the Interrupt Latency of the Real time systems. Interrupt Latency provides an important metric in increasing the performance of the Real Time Kernal. So far the research has been investigated with respect to real-time interrupt latency reduction using non-pre-emptive task scheduling algorithms. A general disadvantage of the non-preemptive discipline is that it introduces additional blocking time in higher priority tasks, so reducing schedulability. If the interrupt latency is increased, the task switching delay shall be increasing with respect to each task. Hence most of the research work has been focussed to reduce interrupt latency by using the Pre-emptive Task scheduling algorithm. Based on the literature survey, A Deadline Monotonic Priority Assignment technique is used to reduce the latency with respect to the deadline. Deferred pre-emption scheduling and Fixed pre-emptive scheduling algorithm are used to reduce the interrupt latencies based on the queue fixed to the priority of the tasks to be handled. Here we suggest a new algorithm named “Priority Preemptive task scheduling algorithm” which preempts and serve the task with highest priority and also concentrates on the low priority tasks during the buffering time of the higher priority tasks.

Quality assurance for the clinical implementation of kilovoltage intrafraction monitoring for prostate cancer VMAT.

Kilovoltage intrafraction monitoring (KIM) is a real-time 3D tumor monitoring system for cancer radiotherapy. KIM uses the commonly available gantry-mounted x-ray imager as input, making this method potentially more widely available than dedicated real-time 3D tumor monitoring systems. KIM is being piloted in a clinical trial for prostate cancer patients treated with VMAT (NCT01742403). The purpose of this work was to develop clinical process and quality assurance (QA) practices for the clinical implementation of KIM. Informed by and adapting existing guideline documents from other real-time monitoring systems, KIM-specific QA practices were developed. The following five KIM-specific QA tests were included: (1) static localization accuracy, (2) dynamic localization accuracy, (3) treatment interruption accuracy, (4) latency measurement, and (5) clinical conditions accuracy. Tests (1)-(4) were performed using KIM to measure static and representative patient-derived prostate motion trajectories using a 3D programmable motion stage supporting an anthropomorphic phantom with implanted gold markers to represent the clinical treatment scenario. The threshold for system tolerable latency is <1 s. The tolerances for all other tests are that both the mean and standard deviation of the difference between the programmed trajectory and the measured data are <1 mm. The (5) clinical conditions accuracy test compared the KIM measured positions with those measured by kV/megavoltage (MV) triangulation from five treatment fractions acquired in a previous pilot study. For the (1) static localization, (2) dynamic localization, and (3) treatment interruption accuracy tests, the mean and standard deviation of the difference are <1.0 mm. (4) The measured latency is 350 ms. (5) For the tests with previously acquired patient data, the mean and standard deviation of the difference between KIM and kV/MV triangulation are <1.0 mm. Clinical process and QA practices for the safe clinical implementation of KIM, a novel real-time monitoring system using commonly available equipment, have been developed and implemented for prostate cancer VMAT.

Development and Implementation of a Linux- Xenomai based Hard Real-Time Device Driver for PCI Data Acquisition System (DAS) Card

This paper elaborates the implementation of a PCI based device driver for a Data Acquisition System (DAS) Card using the RTDM (Real-Time Driver Model) skin over Xenomai kernel, which is integrated with the Linux kernel. A C language kernel module was written for the PCI bus based driver to provide hard real-time capabilities and determinism to any application accessing the DAS card. The PCI DAS card used consisted of 12-bit ADC, 12-bit DAC, Programmable Digital I/O lines (TTL compatible) and Timers/Counters. In order to test all the features of the DAS and the performance of the driver, a test system, consisting of a 3-axis analog accelerometer connected to the ADC of the DAS via a junction box and powered by its DAC, was been constructed. Additionally, a 3-axis digital accelerometer communicated with an AVR development board via I2C in order to generate conditioned input for the programmable digital I/O lines of the DAS card. A graphical tilt measurement application involving real time acquisition of the accelerometers data was implemented using OpenGL. Finally, the driver was thoroughly tested with this arrangement, and the interrupt latencies were noted to be around 4µsec.

Handoff management in communication-based train control networks using stream control transmission protocol and IEEE 802.11p WLANs

Communication-based train control (CBTC) network is an automated control network for railways that ensures the safe operation of rail vehicles using data communications. CBTC networks have stringent requirements for communication availability and latency. Wireless local area network (WLAN) is a popular choice in CBTC networks due to the available commercial-off-the-shelf WLAN equipments. However, handoffs in WLANs may result in communication interruption and long latency in WLANs-based CBTC networks. In this article, we propose a handoff management scheme for CBTC networks using stream control transmission protocol (SCTP) and IEEE 802.11p WLANs to provide high communication availability and low latency in CBTC networks. We formulate the handoff decision problem as a stochastic Semi-Markov Decision Process (SMDP) with the objectives of minimizing the handoff latency and maximizing the SCTP throughput. Simulation results are presented to show that the proposed scheme can significantly improve the handoff performance in CBTC networks.

Handoff Performance Improvements in MIMO-Enabled Communication-Based Train Control Systems

Communication-based train control (CBTC) is an automated control system for railways using data communications. CBTC systems have stringent communication latency requirements. For rail transit systems, wireless local area network (WLAN)-based CBTC is a popular approach due to the wide availability of commercial-off-the-shelf WLAN equipment. However, WLANs were not originally designed for high-speed environments with frequent handoffs, which may result in communication interrupt and long latency. In this paper, we propose a handoff scheme in CBTC systems based on WLANs with multiple-input-multiple-output (MIMO) technologies to improve the handoff latency performance. In particular, we consider channel estimation errors and the tradeoff between MIMO multiplexing gain and diversity gain in making handoff decisions. The handoff problem is formulated as a partially observable Markov decision process (POMDP), and the optimal handoff policy can be derived to minimize the handoff latency. Simulations results based on real field channel measurements are presented to show the effectiveness of the proposed scheme.

Waveperf

Multi-core processors are more and more present in the embedded and real-time world. This paper introduces a code generator software applied to the benchmarking of embedded platforms. This solution creates an application runnable on embedded multicore platform and compliant with both POSIX or Xenomai interface. Running the application outputs an execution trace for each thread of the benchmark. It is also used to check the interruption latency and the preemption of real-time platforms.

On Improving Real-Time Interrupt Latencies of Hybrid Operating Systems with Two-Level Hardware Interrupts

In this paper, we propose to implement hybrid operating systems based on two-level hardware interrupts. We analyze and model the worst-case real-time interrupt latency for RTAI and identify the key component for its optimization. Then, we propose our methodology to implement hybrid operating systems with two-level hardware interrupts by combining the real-time kernel and the time sharing OS (Operating System) kernel. Based on the methodology, we discuss the important issues for the implementation. Finally, we implement a hybrid system called RTLinux-THIN (Real-Time LINUX with Two-level Hardware INterrupts) on the ARM architecture by combining ARM Linux kernel 2.6.9 and μC/OS-II. We conduct experiments on a set of real application programs including mplayer, Bonnie, and iperf, and compare the interrupt latency and interrupt task distributions for RTLinux-THIN (with and without cache locking), RTAI, Linux, and Linux with RT patch on a hardware platform based on Intel PXA270 processor. The results show that our scheme not only provides an easy method for implementing hybrid systems but also achieves the performance improvement for both the time sharing and real-time subsystems.