International Roadmap For Devices And Systems Research Articles

Metrology for 2D materials: a perspective review from the international roadmap for devices and systems.

The International Roadmap for Devices and Systems (IRDS) predicts the integration of 2D materials into high-volume manufacturing as channel materials within the next decade, primarily in ultra-scaled and low-power devices. While their widespread adoption in advanced chip manufacturing is evolving, the need for diverse characterization methods is clear. This is necessary to assess structural, electrical, compositional, and mechanical properties to control and optimize 2D materials in mass-produced devices. Although the lab-to-fab transition remains nascent and a universal metrology solution is yet to emerge, rapid community progress underscores the potential for significant advancements. This paper reviews current measurement capabilities, identifies gaps in essential metrology for CMOS-compatible 2D materials, and explores fundamental measurement science limitations when applying these techniques in high-volume semiconductor manufacturing.

Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping.

n-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance standards. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using electrical measurements backed by atomistic imaging and rigorous analysis, Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ∼10× by aggressively scaling Lch from 1 μm down to ∼20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidation of bilayer WSe2 was used as a p-type dopant. This led to ∼5× improvement in the ON-state performance and ∼9× reduction in the contact resistance. We were able to achieve a median ON-state current as high as ∼10 μA/μm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.

(Invited) High-Performance Field-Effect Transistors Based on Two-Dimensional Materials for VLSI Circuits

Introduction Nowadays, the scaling of silicon very large-scale integration(VLSI) technologies has reached channel thicknesses of 7nm. However, further downscaling becomes increasingly difficult as the gate electrostatics require a substantial reduction of the channel thickness to about a fourth of the gate length. As a result, the actual gate length of high-performance(HP) FETs at the current state-of-the-art amounts to 16nm and is projected to stall at 12nm for the 1.5nm node and the following nodes, according to the International Roadmap for Devices and Systems(IRDS)[1]. For these nodes, two-dimensional(2D) materials could have the potential to replace silicon as the channel material. They can maintain sizable mobilities at atomic thicknesses, thus providing enhanced gate control in stacked channel nanosheet transistor structures[2]. Even though FETs based on 2D materials hold the promise to serve as FETs at the front end of the line, numerous challenges still need to be overcome. Downscaling Dimensions For ultra-scaled device designs, 2D materials can be used as a channel in stacked nanosheet FETs. In such a structure, the 2D material is gated from both sides, as depicted in Fig.1(a). By stacking multiple double-gated channels on top of each other, the required on-current density of around 1mA/μm can be achieved[3]. The first experimental demonstrations have achieved sub-5nm gate lengths[4] or, in a different design, a gate pitch of only 42nm[5], meeting the requirements for the 1.5nm node. While these prototypes show that 2D FETs can be scaled down, they have been fabricated in a laboratory. Many challenges must be overcome before such small devices can be fabricated in industry-compatible batch processes which require a high yield and low variability. Contact Engineering In order to enable sufficiently high on-current densities, small contact resistances to 2D semiconductors are required, which are inhibited by the formation of Schottky barriers at the metal to semiconductor interface. Schottky contacts to 2D materials are so prevalent because there is, on one side, a lack of stable doping schemes, and on the other side, pronounced Fermi-level pinning at the metal-to-semiconductor interface. Semi-metallic bismuth contacts can provide low-resistive contacts to n-type MoS2 FETs, as the bismuth suppresses the metal-induced gap states which pin the Fermi-level[6]. This way, a small contact resistance of 123Ωμm has been achieved, reaching the IRDS limit for the 1.5nm node. While comparable results have been realized for antimony contacts to n-type FETs, low-resistive contacts to p-type FETs are more challenging. Gate Stack Design A good gate stack for 2D FETs must provide excellent gate control while maintaining small gate leakage currents, which requires a capacitive equivalent thickness(CET) smaller than 0.9 nm. At these small CETs, a small gate leakage can only be obtained with a high-dielectric constant gate insulator and sizable band offsets, rendering some insulators, e.g. hexagonal boron nitride, unsuitable. Simultaneously, the gate insulator should form a van-der Waals interface with the 2D semiconductor, as otherwise, interface traps degrade the carrier mobility and the sub-threshold slope[7]. Charge traps within the insulator are the root cause of the limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in pronounced Bias Temperature Instabilities(BTI). The electrical stability can be improved, if the defect bands in the gate insulator are energetically far away from the semiconductor’s conduction and valence band edges, see Fig.1(b)[8]. Conclusions Despite all the progress achieved within the last decade, the challenges for VLSI integration of 2D materials are enormous. First, stacked 2D FETs with scaled dimensions still need to be realized at an industrial scale. Second, despite low contact resistance demonstrations for n-type FETs, the resistances for p-type FETs are one order of magnitude too high. Finally, one of the most serious obstacles is identifying a suitable gate stack. Even though promising combinations of insulators to semiconductors have been suggested, like Bi2O5Se/Bi2O2Se, CaF2/MoS2 or SrTiO3/MoS2, it is at the moment unclear, which of them provides the best performance. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no. 101055379.

(Gordon E. Moore Medal for Outstanding Achievement in SSS&T) Moore’s Law Sustained by Non-Lithographic Technologies

Since G. Moore’s historical observation [1] that the functionality per chip (bits, transistors) as well as MPU performance (clock frequency in MHz × instructions per clock = millions of instructions per second) doubles every 1.5 to 2 years, the semiconductor industry has continued to grow to over 600 G$ in 2022 [2].The IRDS 2022 Roadmap [3] catches the scaling challenges faced for the upcoming decades by the term ‘3D Power Scaling’. This period is the third in a sequence of eras that started early on with straightforward geometrical scaling by continuous shortening of the wavelengths (from regular UV to deep UV/immersion) used in the lithographic patterning of planar transistor structures (Fig. 1a). In the second, almost past ‘equivalent scaling’ era, new superior material properties and critical dimensions nearing single-digit nanometer values could still be realized by cost-effective technology solutions, often in spite of the delay in (EUV) lithography solutions. Ever more complex device architectures requiring extreme edge placement accuracy, layer conformality and shape fidelity in all processing steps (deposition, etching) could be fully 3D-integrated into vertical intra- and inter-chip concepts (Fig. 1b) thus alleviating the need for new capital-intensive lithography tools capable of higher resolution (~ 40% of total tool costs).Figure 2 illustrates the development in the past 65 years of the non-lithographic technologies that have sustained Moore’s Law, as driven by continuous downscaling of CMOS devices. Two extra trends have set in half way (~1993): single-wafer processing and heterogeneous device integration. The latter development, often coined as More than Moore, a term that was introduced in the 2005 ITRS Roadmap, and refers to the silicon-compatible integration of devices with functionalities that do not necessarily scale according to Moore's Law, but provide additional value in different ways. The More-than-Moore approach allows for the incorporation of non-digital functionalities (e.g., RF communication, passive components, power control, sensors, actuators) that can flexibly move from the system board-level into the package (SiP) or onto the chip (SoC).We will discuss a kaleidoscopic view of the author’s activities in Rapid Thermal Processing, RIE etching for TSVs, RF-SIP integration of passives, and Atomic Layer Processing (deposition, etch, and cleaning). In sub-10 nm scaling and fabrication of 3D architectures, especially the techniques of ALD and ALE have manifested to cost-effectively bridge the record incubation time needed to bring EUV technology from prototype to commercial use. More importantly, these unique techniques can be used to create advanced devices in dedicated isotropic (thermal and radical-enhanced) and anisotropic (directional and ion-enhanced) processing modes. Here, energetic species (radicals and/or ions in a plasma) are used in one or two steps, with the ions yielding anisotropic profiles (used in FinFET logic and 3D NAND memory), and neutrals and radicals yielding isotropic profiles used to deposit or etch the features in horizontal nanowires, nanosheets and ‘forksheets’ in GAA-FETs.1. G. Moore, Cramming more components onto integrated circuits, Electronics 38(8), (1965) 114-118.2. https://www.semiconductors.org/global-semiconductor-sales-increase-24-year-to-year-in-october-annual-sales-projected-to-increase-26-in-2021-exceed-600-billion-in-2022/3. International Roadmap for Devices and Systems (IRDS™) 2022 Edition - IEEE IRDS™. Fig. 1. a) Different scaling ages for device manufacturing; b) the planar-to-GAA transition; after [3]. Fig. 2. Historic and future perspectives of non-lithographic key technologies in IC scaling. Figure 1

Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System.

Multi-gate field effect transistors (FETs) such as FinFETs are severely affected by short-channel effects (SCEs) below 14 nm technology nodes, with even taller fins incurring fringing capacitances. This leads to performance degradation of the devices, which inhibits further scaling of nanoFETs, deterring the progress of semiconductor industries. Therefore, research has not kept pace with the technological requirements of the International Roadmap for Devices and Systems (IRDS). Thus, the development of newer devices with superior performances in terms of higher ON currents, acceptable leakage currents and improved SCEs is needed to enable the continuance of integrated circuit (IC) technologies. The literature has advocated integration of strained-silicon technology in existing FinFETs, which is highly effective in enhancing ON currents through the strain effect. However, the ON currents can also be amplified by intensifying the number of fins in trigate (TG) FinFETs. Thus, three-fin TG quantum (Q)-FinFETs, using a novel tri-layered strained-silicon channel, are deployed here at 10 nm and 8 nm channel lengths. Threshold voltage is calculated analytically to validate the designs. The electrical parameters and quantum effects of both devices are explored, analysed and compared with respect to existing heterostructure-on-insulator (HOI) FinFETs and the proposed existing standard requirement of IRDS 2022 for a 3 nm technology node. The comparisons demonstrated a significant increase in the drive currents upon employing three fins of the same dimensions (8 nm gate length) and specifications in a device-based system. The performance is augmented in contrast to the 3 nm technology node device of IRDS 2022, with SCEs within the limits. Thus, employing a tri-layered strained-silicon channel system in each fin allowed for forming a three-fin Q-FinFET that, in our opinion, is the technique for consolidating the performance of the devices and enabling future generation device for faster switching operation in a sub-nano regime.

Ballistic two-dimensional InSe transistors.

The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. 1). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm-1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V-1. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.

2D fin field-effect transistors integrated with epitaxial high-k gate oxide.

Precise integration of two-dimensional (2D) semiconductors and high-dielectric-constant (k) gate oxides into three-dimensional (3D) vertical-architecture arrays holds promise for developing ultrascaled transistors1-5, but has proved challenging. Here we report the epitaxial synthesis of vertically aligned arrays of 2D fin-oxide heterostructures, a new class of 3D architecture in which high-mobility 2D semiconductor fin Bi2O2Se and single-crystal high-k gate oxide Bi2SeO5 are epitaxially integrated. These 2D fin-oxide epitaxial heterostructures have atomically flat interfaces and ultrathin fin thickness down to one unit cell (1.2 nm), achieving wafer-scale, site-specific and high-density growth of mono-oriented arrays. The as-fabricated 2D fin field-effect transistors (FinFETs) based on Bi2O2Se/Bi2SeO5 epitaxial heterostructures exhibit high electron mobility (μ) up to 270 cm2 V-1 s-1, ultralow off-state current (IOFF) down to about 1 pA μm-1, high on/off current ratios (ION/IOFF) up to 108 and high on-state current (ION) up to 830 μA μm-1 at 400-nm channel length, which meet the low-power specifications projected by the International Roadmap for Devices and Systems (IRDS)6. The 2D fin-oxide epitaxial heterostructures open up new avenues for the further extension of Moore's law.

Device structure and fabrication process for silicon spin qubit realizing process-variation-robust SWAP gate operation

In this study, we propose technologies for the device structure, gate fabrication process, and back-bias-assisted operation of Si spin qubits to realize the high robustness of the two-qubit SWAP gate operation against process variations. We performed quantum device simulations for MOS-type two-qubit devices and verified the benefits of these technologies on the SWAP gate fidelity. We clarified that these technologies significantly improve the robustness of the SWAP gate operation against process variations and achieve a 6σ-yield SWAP gate operation with 99% fidelity, assuming device size fluctuation of the International Roadmap for Devices and Systems (IRDS) target for 2022. The proposed technologies provide a solution for completing a universal quantum gate set for realizing universal quantum computers with silicon.

Extreme Anisotropic Dispersion and One-Dimensional Confined Electrons in 2-D SiP₂ FETs With High Transmission Coefficients

2-D semiconductors are promising Si alternatives for channels in next-generation electronic devices. Considering the 2-D SiP2 with unique dispersion at the band edge and intrinsic P–P chains with 1-D confined electrons, we provide a comprehensive investigation on the electronic and ballistic transport properties of SiP2. Based on first-principle and ballistic quantum transport simulations, the 2-D SiP2 exhibits a strong anisotropy in both geometric structures and electronic properties, playing a critical role in the anisotropy of transmission path and device performance for SiP2 field-effect transistors (FETs). Considering the ultrahigh saturation current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {sat}}$ </tex-math></inline-formula> ) of SiP2 FETs in along-chain direction, the transfer characteristic with different gate lengths (3–12 nm) is calculated to thoroughly evaluate the performance. As a result, 5–12 nm SiP2 n-FETs with underlap (UL) configuration can fulfill the International Technology Roadmap for Semiconductors (ITRS) and International Roadmap for Devices and Systems (IRDS) goals, showing an ultrahigh ON-state current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3420 ~{\mu } \text{A}/ {\mu } \text{m}$ </tex-math></inline-formula> with 10 nm gate length. In addition, the figures of merits, such as delay time and power dissipation, are comprehensively assessed, proving the fast-switching and low-energy consumption ability of SiP2 FETs. Hence, our study demonstrates the great potential of 2-D SiP2 for future competitive electronic devices.

Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method

In the past 20 years, semiconductor manufacturing technology has advanced rapidly, but the advancement of integrated circuit (IC) testers has been slow. Using obsolete testers to inspect advanced wafers has become a significant challenge for test manufacturers. In this research, we used DITM (digital IC testing model) to discuss the impact of the test guardband (TGB) on quality and yield. Considering the interaction between semiconductor fabrication capability parameters and test capability parameters, we proposed an estimation method [deductive estimation method (DEM)] to analyze the electrical distribution changes of products after chip production and deduce the yield of future products. The deductive estimation method can correctly depict the future test yield [Formula: see text] curve using the chip frequency data published by IRDS (International Roadmap for Devices and Systems) in 2017. Furthermore, test manufacturers can measure whether the current test capabilities can cope with future semiconductor chip manufacturing capabilities by predicting the trends. Next, test manufacturers can maintain high-quality and high-yield chip output by pre-adjusting the hardware testing capabilities of ATE (automated test equipment) or proposing more effective chip testing methods.

Device Performance of Double-Gate Schottky-Barrier Graphene Nanoribbon Field-Effect Transistors with Physical Scaling

Moore’s law is approaching its limit due to various challenges, especially the size limit of the transistors. The International Roadmap for Devices and Systems (IRDS), the successor of International Technology Roadmap for Semiconductors (ITRS), has included 2D materials as an alternative approach for the More-than-Moore nanoelectronic applications. Among the 2D materials, graphene nanoribbons (GNRs) have been widely used as the alternative channel materials of field-effect transistors (FETs). In this paper, the impacts of physical scaling on the device performance of double-gate Schottky-barrier GNR FETs (DG-SB-GNRFETs) are investigated by using NanoTCAD ViDES simulation tool based on the tight-binding Hamiltonian and self-consistent solutions of 3D Poisson and Schrödinger equations with open boundary conditions within the nonequilibrium Green’s function formalism. The extracted device performance parameters include the subthreshold swing and on-to-off current ratio. The results suggest that the performances of DG-SB-GNRFETs are strongly dependent on their physical parameters, especially the widths of the GNRs.

Discovery of Clustered-P1 Borophene and Its Application as the Lightest High-Performance Transistor

The two-dimensional network of boron atoms (borophene) has attracted attention for its ultralow molar mass and remarkable polymorphism. Synthesized polymorphs of borophene (striped, β12, χ3, and honeycomb), so far, are all found to be metallic. Employing a genetic algorithm-based structure searching technique, here we discover an allotrope, clustered-P1, which is located very close to the global energy minimum. Clustered-P1 exhibits a bulk silicon-like band gap (1.08 eV) with symmetric effective masses (∼0.2 m0) for electrons and holes along the transport direction. Phonon dispersion and beyond room-temperature ab initio molecular dynamics studies further confirm its excellent dynamic and structural stability. Since two-dimensional semiconductors are promising silicon alternatives for complementary metal-oxide semiconductor (CMOS) technology extension, we further investigate the characteristics of clustered-P1-based transistors using self-consistent quantum transport models for channel lengths of 10-3 nm. The performance of these devices has been found to be balanced for p- and n-type transistors and meets the requirements of the International Roadmap for Devices and Systems (IRDS). Our study may aid in the experimental realization of the lightest high-performance transistor.

(Invited, Digital Presentation) Heterogeneous Integration of Ultrahigh-Κ Single-Crystalline SrTiO3 Membranes for Two-Dimensional Electronics

Even though competitive 2D field-effect transistors (FETs) with the scaled channel dimensions have been demonstrated, it still is a challenge to integrate 2D semiconductors and high-κ dielectrics without deteriorating their interfaces, while decreasing capacitance equivalent thickness (CET) of dielectrics to maintain the gate controllability. In particular, the dielectric/channel interface is one of the predominant factors to affect device performance, including carrier mobility, switching behavior, and drifts of device parameters. This is often caused by the nature of dielectrics used, and the integrating methodologies applied.Typically, high-κ dielectrics used in silicon technology (i.e., Al2O3 and HfO2) are inherited by 2D FETs. The amorphous nature of these oxides makes the elimination of charge scattering and trapping sites at the dielectric/channel interfaces extremely difficult, not to mention that the direct deposition of dielectrics usually damages the 2D channel and results in poor uniformity in sheer thickness. Some interfacial passivation layers and processes have been developed, but they lead to thickening overall CET instead. Alternative approaches with the crystalline dielectric materials such as multilayer hBN and epitaxial calcium fluoride (CaF2), whose surfaces are well-constructed and atomic-flat, have demonstrated the competitive advantages of crystalline dielectric over the conventional amorphous oxides in spite of relatively lower κ values.Here, we demonstrate ultra-scaled 2D FETs with desirable sub-1 nm CET through heterogeneous integration of monolayer CVD MoS2 and quasi-2D single-crystalline SrTiO3 membranes, where the optimized SrTiO3 gate dielectrics exhibit a low gate leakage (J leak < 10-2 A/cm2 at 2.5 MV/cm). Typical transistors manifest good reliability and competitive performance characteristics, including steep subthreshold swings (SS) down to ~70 mV dec-1 and ON/OFF current ratios up to 107, matching low-power specifications suggested by the latest International Roadmap for Devices and Systems (IRDS). In addition, the van der Waals (vdW) interface between quasi-2D dielectrics and 2D semiconductors moderates the unfavorable fringing-induced barrier lowering (FIBL) effect occurring in ultra-scaled Si transistors with very high-κ dielectrics, which broadens the dielectric selection in 2D electronics for future technology node.

High-throughput design of functional-engineered MXene transistors with low-resistive contacts

Two-dimensional material-based transistors are being extensively investigated for CMOS (complementary metal oxide semiconductor) technology extension; nevertheless, downscaling appears to be challenging owing to high metal-semiconductor contact resistance. Here, we propose a functional group-engineered monolayer transistor architecture that takes advantage of MXenes’ natural material chemistry to offer low-resistive contacts. We design an automated, high-throughput computational pipeline that first performs hybrid density functional theory-based calculations to find 16 sets of complementary transistor configurations by screening more than 23,000 materials from an MXene database and then conducts self-consistent quantum transport calculations to simulate their current-voltage characteristics for channel lengths ranging from 10 nm to 3 nm. Performance of these devices has been found to meet the requirements of the international roadmap for devices and systems (IRDS) for several benchmark metrics (on current, power dissipation, delay, and subthreshold swing). The proposed balanced-mode, functional-engineered MXene transistors may lead to a realistic solution for the sub-decananometer technology scaling by enabling doping-free intrinsically low contact resistance.

Impact of unpreventable induced interface trapped charges on HZO based FDSOI NCFET

In this paper, the effect of oxide-semiconductor interface trapped charges on the performance of 22-nm Fully Depleted Silicon on Insulator (FDSOI) Negative Capacitance FET (NCFET) has been systematically investigated. Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) type NCFET with zirconium doped HfO2 (HZO) as the ferroelectric material is considered for this work. The simulation of the underlying Metal-Insulator-Semiconductor (MIS) structure has been carried out in a well-calibrated TCAD environment to extract the gate charge. Which is subsequently used to solve 1D Landau-Khalatnikov (1D-LK) model to find the voltage across ferroelectric capacitor. The presence of trap charges is unavoidable in modern devices, which affects the charge balance equation as well as the performance & reliability of the device. NCFET being one of the potential candidates to be adopted by industry for ultra-low power applications in the future according to the International Roadmap for Devices and Systems (IRDS), investigation of trap charges becomes crucial. Due to its multilayer stacking, the transfer characteristics are analyzed for various ferroelectric thicknesses with exhibition of an intersection point, which is demonstrated for the first time. Simulation of variation of device performance metrics like minimum sub-threshold swing (min. SS), transconductance (gm), off-state drain current (Ioff) & amplification factor (AV) are analyzed and compared for various interface trapped charge densities. It is predicted that the device performance either enhances or degrade depending on the type of trapped charges present.

A Machine Learning Approach for Optimization of Channel Geometry and Source/Drain Doping Profile of Stacked Nanosheet Transistors

Complex nonlinear dependence of ultra-scaled transistor performance on its channel geometry and source/drain (S/D) doping profile bring obstacles in the advanced technology path-finding and optimization. A machine learning-based multi-objective optimization (MOO) workflow is proposed to optimize the sub-3-nm node gate-all-around (GAA) three-layer-stacked nanosheet transistors (NSFETs) accounting for the key performance knob of channel geometry and S/D doping profile. The artificial neural network (ANN) is trained to learn the compact current–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> ) relationship of NSFETs from 3-D technology computer-aided design (TCAD) simulation results. Based on the artificial neural network (ANN) model, MOO between threshold swing, on–off ratio, and ON-state current of NSFETs is performed with adaptive weighted sum theory. The proposed workflow efficiently suggests an optimized design window of channel geometry and doping profile of NSFETs. The proposed devices satisfy the 2025 International Roadmap for Devices and Systems (IRDSs) target in terms of electrical characteristics for digital circuits.

High‐Performance p‐type 2D FET Based on Monolayer GeC with High Hole Mobility: A DFT‐NEGF Study

Abstract2D materials are identified as Si alternatives for channels in next‐generation electronic devices. However, lack of high‐performance (HP) p‐type field‐effect transistors (FETs) acts as a block to the development of efficient complementary circuits. Here, p‐type monolayer GeC with planar structure is evaluated as a promising channel material to resolve the corresponding problems. The monolayer GeC possesses a direct bandgap of 2.07 eV with high hole mobility up to 6600 cm2 V–1 s–1. Coupling with ballistic quantum transport simulations, the results show that both n‐ and p‐FETs can hold the on‐currents exceeding 1200 µA µm–1 for HP devices. Particularly, for p‐type, the on‐currents with the channel shrinking from 10 to 3 nm can reach as high as 2991—1660 µA µm–1, which is of great value for the design of complementary circuits in 2D electronics. In addition, the figures of merits for GeC FETs, such as delay time, power dissipation, and energy‐delay product, are also assessed, fulfilling the demands of the International Technology Roadmap for Semiconductors (ITRS) and the International Roadmap for Devices and Systems (IRDS) for HP applications. Hence, this study demonstrates great potential of 2D GeC for future competitive electronic devices.

High-Performance and Low-Power Transistors Based on Anisotropic Monolayer β - TeO2

Two-dimensional (2D) semiconductors offer a promising prospect for high-performance and energy-efficient devices especially in the sub-10-nm regime. Inspired by the successful fabrication of 2D \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ and the high on:off ratio and high air stability of fabricated FETs [Zavabeti et al., Nat. Electron. 4, 277 (2021)], we provide a comprehensive investigation of the electronic structure of monolayer \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ and the device performance of sub-10-nm MOSFETs based on this material. The anisotropic electronic structure of monolayer \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ plays a critical role in the anisotropy of transport properties for MOSFETs. We show that the 5.2-nm gate-length n-type MOSFET holds an ultrahigh on-state current exceeding 3700 \textmu{}A/\textmu{}m according to International Roadmap for Devices and Systems (IRDS) 2020 goals for high-performance devices, which is benefited by the highly anisotropic electron effective mass. Moreover, monolayer \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ MOSFETs can fulfill the IRDS 2020 goals for both high-performance and low-power devices in terms of on-state current, subthreshold swing, delay time, and power-delay product. This study unveils monolayer \ensuremath{\beta}-${\mathrm{Te}\mathrm{O}}_{2}$ as a promising candidate for ultrascaled devices in future nanoelectronics.

Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit.

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length.

At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.