Internal Registers Research Articles

Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors

This paper presents an enhanced tool flow and hardware to allow a host CPU to exploit the timing margins available on a FPGA fabric to improve its performance or reduce its energy and power requirements. Two different case studies are considered to demonstrate the performance gains and energy reduction possible in realistic scenarios. The first case study presents a video fusion system with hardware acceleration. The video fusion application is based on Dual-Tree Complex Wavelet Transforms (DT-CWT) that are mapped to a hardware accelerator using high-level synthesis tools. The hardware netlist is processed and in-situ detectors are automatically added to monitor and pre-detect timing failures occurring in the critical path flip-flops. In the second case study the tool flow is extended to support cases where the critical paths terminate in memory blocks with internal registers hidden from the user. A soft-core multiprocessor implemented in the FPGA is used to illustrate the additional challenges and proposed solution. In both cases the host CPU can control the voltage and frequency of the FPGA and compute to the performance or energy limit obtaining around 70% increase in performance or reduction in energy. Intermediate solutions that trade different levels of performance for energy are also possible. The system exhibits excellent energy proportional computing characteristics and can adapt its operating point to complete a task within a given time budget so that only the minimum level of energy is used.

Improve Productivity through Reducing MBT Application Time Using Multi Bad Block Management DFT

Recently, storage market has been shifting from hard disk to SSD, and the importance of NAND flash memory, which plays a key role as a storage media in the SSD, is also increasing. Accordingly, in the manufacturing phase, the test cost of NAND flash memory is getting larger as the density of NAND flash memory is increasing. In this paper, we propose a scheme for DFT(Design for Testability) that can reduce the NAND flash test cost and apply it to the actual MBT(Monitoring Burn-in Test) manufacturing process to prove improvements in the manufacturing cost. There are 3 steps (DC/MBT/POB) between package process and shipment. The purpose of 3 steps is to evaluate the characteristics and to ensure the reliability. MBT equipment stresses to induce early failure of marginal devices in amount of time at hot temperature. Therefore we can reduce defective products in early stage. MBT is essential process in manufacturing NAND flash memory. Therefore, reducing MBT process cost has been a big issue. Using the characteristics of MBT application and NAND flash memory, the DFT method is devised. NAND flash memory always has bad blocks as part of the total blocks. User can not use bad blocks. Therefore it is necessary routine to manage bad blocks when devices are tested. MBT equipment consists of 48 slots and each slot has 64ea I/O channels. If a device has 8ea I/O pins, it can be tested just 8ea devices per slot concurrently. In order to test more than 8ea devices each slot, the test should be conducted in several times. This concept is called “scan”. Increasing test time is caused by increasing the total scan times in accordance with MBT structural problems. Scan and slot structure acts as a factor enabling the massive quantity test. Thus the total scan loop times take up a large portion MBT application time, we are studying ways to reduce the total scan loop times. We devised a DFT method for managing bad block efficiently. This DFT method is called multi bad block management, the details are as follows. Previously in order to find bad blocks, MBT equipment loops scan at every single block to determine pass or fail. We suggest that the newly proposed method is storing pass/fail data of multiple blocks in NAND flash memory internal register. And it is added to the accumulator to determine pass/fail of every multiple blocks rather than single block. It is possible that scan doesn`t loop not single block but every multiple blocks. As a result, it can reduce total scan loop times as follows. As is : (The Number of Total Blocks) x Scan Loop To be : (The Number of Total Blocks/64) x Scan Loop There are a large number of internals latches for pass /fail in NAND flash memory. Toggling RE(read-enable) signal outputs continuously multiple blocks Pass/Fail bit which is stored in the latch. It reduces the scan loop times of MBT, which can reduce system time. It enables test cost reduction and increases productivity due to reduced overall test time, and improves test efficiency. Status parity of 64ea blocks pass/fail parity are stored in chip for shorten the test time in MBT process. When applied to 128Gb NAND flash memory, we could reduce from 21.5 hours to 18.5 hours about 14% test time. If there are more the pass/fail latches, it can further reduce the test time. However because of the area overhead, we limit to status of 64ea blocks. With multi bad block management DFT techniques, we can reduce NAND flash memory test cost of the SSD. Also, if applied products are developed in the future, it is expected to continue to be able to see the effect.

On the Security of a Universal Cryptocomputer: the Chosen Instruction Attack

The ultimate goal of private function evaluation is the complete outsourcing of processing tasks to distrusted platforms (such as clouds), so that arbitrary functions can be evaluated without any leakage of secret information. Several successful concepts have been proposed in the past, the most striking one having been fully homomorphic encryption besides the well-known garbled circuits and multiparty computation. In this paper, we look at an idealized model of outsourced computation, which we call a cryptocomputer . This is a (theoretical) machine that works exactly like a real-life computer in the sense of understanding a standard assembly language, but retaining all its internal signals, registers, and memory encrypted at all times. The encryption is assumed under a key that is unknown to the attacker, and taken as secure (in any cryptographically meaningful way), so that no leakage of information from any ciphertext can be expected from programs with reasonable (polynomial) time complexity. Unfortunately, such a cryptocomputer is necessarily insecure, irrespectively of how the encryption looks like. In particular, we explicitly do not assume any specific form of security (chosen-ciphertext or other) or (a)symmetry of encryption; our attack works only on ciphertexts and makes no assumptions whatsoever on the encryption. We prove insecurity of the cryptocomputer by taking the encryption as a black box, and show how to decipher every signal in the computer by pure virtue of submitting proper instructions for execution. Our attack falls into the general category of side-channel attacks, however unlike other related attacks, does neither exploit physical nor any logical characteristics of the underlying platform (besides the execution flow being observable). Somewhat surprisingly, it turns out that although the problem that we consider is cryptographic, it seemingly has no cryptographic solution and apparently calls for an interdisciplinary approach from new directions.

Design of High-Performance HOG Feature Calculation Circuit for Real-Time Pedestrian Detection

This paper proposes the design of high-performance histogram of oriented gradient (HOG) feature calculation circuit for real-time pedestrian detection. By utilizing thoroughly analyzed results of the operations for overlapping blocks and windows and by managing internal memories and registers to store the intermediate results of HOG feature efficiently, not only all redundant operations are totally removed but also trilinear interpolation technique is successfully applied in the proposed circuit. The proposed circuit can process variable sizes of input image up to full high-definition (HD) image and it supports two types of detection window and color format of input image. In order to accelerate the processing time, the proposed circuit adopts the parallel architecture with pipelines, and the external memory bandwidth is minimized by the efficient management of internal memories and registers. The circuit size is reduced by sharing the circuit resources for the common operations and by minimizing the required storage spaces. Even though a large amount of computations is required due to trilinear interpolation, the proposed circuit can process full HD images in real time, assuming a scaling factor of 0.9. Therefore, it can be used for real-time pedestrian detection in many applications.

Context-Adaptive Binary Arithmetic Coding With Fixed-Length Codewords

Context-adaptive binary arithmetic coding is a widespread technique in the field of image and video coding. Most state-of-the-art arithmetic coders produce a (long) codeword of a priori unknown length. Its generation requires a renormalization procedure to permit progressive processing. This paper introduces two arithmetic coders that produce multiple codewords of fixed length. Contrary to the traditional approach, the generation of fixed-length codewords does not require renormalization since the whole interval arithmetic is stored in the coder’s internal registers. The proposed coders employ a new context-adaptive mechanism based on variable-size sliding window that estimates with high precision the probability of the symbols coded. Their integration in coding systems is straightforward as demonstrated within the framework of JPEG2000. Experimental tests indicate that the proposed coders are computationally simpler than the MQ coder of JPEG2000 and the M coder of HEVC while achieving superior coding efficiency.

VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD’s). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500eV and 50keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6µs to 6.6µs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35µm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200µm×500µm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6µs peaking time and room temperature is measured and the linearity error is between −0.9% and +0.6% in the whole input energy range. The total power consumption is 481µW and 420µW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD’s shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

Rol del estado como autoridad reguladora de ensayos clínicos en el Perú

This article sheds the light on historical review of the clinical trials regulatory process to the publication of the Clinical Trials Regulation in Peru, by Supreme Decree 017-2006-SA. In this context, that Regulation was amended within one year, with many critics including from the Ombudsman. It also considers the achievements as a regulatory authority that has strengthened its steering and its main objective of protecting the rights, safety and welfare of human subjects in clinical trials. Those achievements are: the internal register of clinical trials, strengthening inspections on all stakeholders that take part in research, the Notification System of Serious Adverse Events (REAS-NET), the publication of the Guideline: “Ethical, Legal and methodology in clinical trials for use of the Ethical Review Board “ which won an international award; the 1st prize in the category of fizcalization and accomplishment of the law by the Good Practice of Public Management: “Protecting the rights of human subjects in experimental studies”, the publication of the new Manual of Procedures for Clinical Trials and the implementation Plan of the National Bioethics Network in Peru.

Hardware support for memory protection in sensor nodes

With reference to the typical hardware configuration of a sensor node, we present the architecture of a memory protection unit (MPU) designed as a low-complexity addition to the microcontroller. The MPU is aimed at supporting memory protection and the privileged execution mode. It is connected to the system buses, and is seen by the processor as a memory-mapped input/output device. The contents of the internal MPU registers specify the composition of the protection contexts of the running program in terms of access rights for the memory pages. The MPU generates a hardware interrupt to the processor when it detects a protection violation. The proposed MPU architecture is evaluated from a number of salient viewpoints, which include the distribution, review and revocation of access permissions, and the support for important memory protection paradigms, including hierarchical contexts and protection rings.

XCS with an internal action table for non-Markov environments

To cope with sequential decision problems in non- Markov environments, learning classifier systems using the internal register have been proposed. Since, by utilizing the action part of classifiers, these systems control the internal register in the same way as choosing actions to the environment, they do not always work well. In this paper, we develop an effective learning classifier system with two different rule sets for internal and external actions. The first one is used for determining internal actions, that is, rules for controlling the internal register. It provides stable performance by separating control of the internal register from the action part of classifiers, and it is represented by “If [external state] & [internal state] then [internal action],” and we call a set of the first rules the internal action table. The second one is for selecting external actions as in the classical classifier system, but its structure is slightly different with the classical one; it is represented by “If [external state] & [internal state] & [internal action] then [external action].” In the proposed system, aliased states in the environment are identified by observing payoffs of a classifier and referring to the internal action table. To demonstrate the efficiency and effectiveness of the proposed system, we apply it to woods environments which are used in the related works, and compare the performance of it to those of the existing classifier systems.

Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures

Trivium is a synchronous stream cipher using three shift registers. It is designed to have a simple structure and runs at high speed. A scan-based side-channel attack retrieves secret information using scan chains, one of design-for-test techniques. In this paper, a scan-based side-channel attack method against Trivium using scan signatures is proposed. In our method, we reconstruct a previous internal state in Trivium one by one from the internal state just when a ciphertext is generated. When we retrieve the internal state, we focus on a particular 1-bit position in a collection of scan chains and then we can attack Trivium even if the scan chain includes other registers than internal state registers in Trivium. Experimental results show that our proposed method successfully retrieves a plaintext from a ciphertext generated by Trivium.

A Computational Method of Real-valued Discrete Fourier Series Transform (real-DFST) and Application

In this paper, we propose a real-valued discrete Fourier series transform (real-DFST) and a computational method for the circular cross correlation. For images, the real-DFST presents the sub elements of frequency components in the DFT. And the space of the real-DFST is a real number space, therefore the real-DFST can be represented with a memory space for image-size real numbers. The real-DFST is a memory saving model for real-valued data and is faster than the DFT in computation. These advantages are important to implement hardware and to compute with large sequences/images. In implementation of system, proposed computational method could be used to enhance their systems through the better MCU computation-time by internal register memory or cache memory. According to increase the size of images, memory saving model is required necessarily. Experiments are suggested for the circular cross correlation processing in the real-DFST and experiments show the computational result for images.

연판정 Reed-Solomon 리스트 디코딩을 위한 저복잡도 Interpolation 구조

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

TCH-002 Analysis of Dispensing Logistics Processes Carried Out by Semiautomatic Carousel Systems

BackgroundHospital Pharmacy Services work hard at logistics to supply medicinal products to inpatients. This prompted the need to modernise the technical resources and logistical processes with a semiautomatic carousel system...

SAO의 성능개선을 위한 저면적 하드웨어 설계

In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing CU to reduce the hardware area and uses internal registers to support CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

Rol del estado como autoridad reguladora de ensayos clínicos en el Perú

This article sheds the light on historical review of the clinical trials regulatory process to the publication of the Clinical Trials Regulation in Peru, by Supreme Decree 017-2006-SA. In this context, that Regulation was amended within one year, with many critics including from the Ombudsman. It also considers the achievements as a regulatory authority that has strengthened its steering and its main objective of protecting the rights, safety and welfare of human subjects in clinical trials. Those achievements are: the internal register of clinical trials, strengthening inspections on all stakeholders that take part in research, the Notification System of Serious Adverse Events (REAS-NET), the publication of the Guideline: "Ethical, Legal and methodology in clinical trials for use of the Ethical Review Board" which won an international award; the 1st prize in the category of fizcalization and accomplishment of the law by the Good Practice of Public Management: "Protecting the rights of human subjects in experimental studies", the publication of the new Manual of Procedures for Clinical Trials and the implementation Plan of the National Bioethics Network in Peru.

FPGA Implementation of Interrupt Controller (8259) by using Verilog HDL

Priority Interrupt Controller is a hardware designed chip which acts as an overall system manager to efficiently handle the multiple interrupts that tend to occur from the varied number of peripheral devices. Hence, it relieves the systems CPU from the task of polling in a multilevel priority system. This paper deals with implementation of a Priority Interrupt Controller using Verilog language. During the implementation, the Verilog code has been written for all the internal registers of the Priority Interrupt Controller so that it can accomplish its task of prioritizing the various interrupts and thereby increasing the efficiency of the processor. In this paper the entire functional block was sub divided into various modules like vector address module, command register module, mask register module and finally it was integrated into a single unit to accomplish specified tasks. In the present work the Priority Interrupt Controller was made to operate in three different modes-Fully Nested Mode, Rotating Priority Mode, and Special Mask Mode.

Detection of Electromagnetic Interference in Microcontrollers Using the Instability of an Embedded Phase-Lock Loop

This paper presents a combined hardware-software mechanism for the detection of electromagnetic interference of a microcontroller (μC) in daily usage. This detection mechanism is based on the instability of phase-lock loop embedded in the target μC. It can detect the presence of EMI with higher sensitivity than polling the hardware status of the μC internal registers and thus provides a better detection margin within the 10 kHz to 1 GHz EMI frequency range. Despite its relative slowness and its resource consumption, it is very robust, can be implemented in virtually any application software, and does not require any electromagnetic compatibility test equipment.

Design and Implementation of Debugging Structure in Full-Custom CPU

With the development of integrated circuit technology, it is more and more difficult for debugging circuits. Generally, to achieve a powerful debugging capability of circuits is often at the expense of larger cost of hardware overhead .This paper propose a method of debugging structure designed in full-custom CPU based on scan-set testability methods and combed with the boundary-scan technology. This debugging structure can reduces much scan chains hardware overheads and is applicable to all general-purpose CPU chips. Moreover, it owns a powerful debugging capability which is observing and controlling the internal registers of circuits from JTAG port. This structure only increases the difficulty of the circuit logic design, but greatly decreases the cost of hardware.

Digit-Serial Pipeline Sorter Architecture

This paper presents the VLSI architecture design of pipeline sorter which is suitable for the fast sorting of the continuous serial input data stream. By decomposing the Batcher's merge-sort process into a network of compare-and-swap (C&S) operations, two different styles of pipeline architectures based on the feedback and feed-forward data shuffling modules can be first achieved. However, both architectures suffer the low hardware utilization due to the discrepancy of input sample rate and internal processing rate. Therefore, this paper further proposes a novel digit-serial pipeline sorter architecture by dividing the data into two sub-words. In addition, the most-significant half-word data are processed first in order to reduce the internal register overhead incurred in the C&S unit. Our experimental results show that about 50% saving of gate counts can be achieved by the digit-serial approach.

A GPU-based Real-time Software Correlation System for the Murchison Widefield Array Prototype

ABSTRACTModern graphics processing units (GPUs) are inexpensive commodity hardware that offer Tflop/s theoretical computing capacity. GPUs are well suited to many compute-intensive tasks including digital signal processing. We describe the implementation and performance of a GPU-based digital correlator for radio astronomy. The correlator is implemented using the NVIDIA CUDA development environment. We evaluate three design options on two generations of NVIDIA hardware. The different designs utilize the internal registers, shared memory, and multiprocessors in different ways. We find that optimal performance is achieved with the design that minimizes global memory reads on recent generations of hardware. The GPU-based correlator outperforms a single-threaded CPU equivalent by a factor of 60 for a 32-antenna array, and runs on commodity PC hardware. The extra compute capability provided by the GPU maximizes the correlation capability of a PC while retaining the fast development time associated with using standard hardware, networking, and programming languages. In this way, a GPU-based correlation system represents a middle ground in design space between high performance, custom-built hardware, and pure CPU-based software correlation. The correlator was deployed at the Murchison Widefield Array 32-antenna prototype system where it ran in real time for extended periods. We briefly describe the data capture, streaming, and correlation system for the prototype array.