Internal FIFO Research Articles

Multi-Channel Data Acquisition System Based on FPGA and STM32

In order to realize the acquisition and storage of underwater acoustic signals for aiming at the requirements of multi-channel, low power consumption and small volume for underwater receiver extension of sonar system, a multi-channel signal acquisition and storage system based on FPGA and STM32 with variable number of working channels and sampling frequency is designed, in which the system is consisted of 8 pieces, 8 channel and 24 bits high dynamic range Δ-Σ ADS1278 ADC chip to synchronous multi-channel analog signal acquisition. FPGA, as the acquisition sequence and logic control, reads and collates the ADC chip data and writes it into the internal high-capacity FIFO, and adds corresponding operations according to the characteristics of FIFO in an application. SMT32 single-chip microcomputer reads the FIFO data through the high-speed SPI interface with FPGA and writes the multi-channel data into the high-capacity SD card. The testing results have verified that the system has characteristics such as stable and reliable, easy configuration, low power consumption, can guarantee the multichannel data serial transmission, storage, accurate, up to 64 analog signals at the same time the real-time collection and storage, top 20 kHz sampling rate, the system total power of the system of about 3W, data rates up to 100 Mb/s, fully meet the needs of underwater sound acquisition system.

Bi-modal macroscopic traffic dynamics in a single region

Bi-modal or 3D-MFD relates the accumulation of cars, buses to total production at the network level. The current work provides a detailed discussion of extended MFD-based models namely, accumulation-based and trip-based models that accounts for bi-modal flows through 3D-MFD. In addition, delay accumulation-based models, also known as exit-flow models in classical traffic flow theory, are revisited. Fundamental modeling differences between different MFD-based models are illustrated using a benchmark test case. A new FIFO-based entry flow function is also proposed in order to address the inconsistencies of the conventional entry flow function in the context of the 3D-MFD case. A novel weak internal FIFO discipline is proposed to circumnavigate the violation of internal FIFO order during network unloading in the delay accumulation-based model. MFD-based models are verified using the solutions of micro-simulations performed on an idealized grid network. The importance of separating the 3D-MFD into partial car and bus 3D-MFDs is highlighted. Moreover, it is also shown that partial bus 3D-MFD should be further split when dedicated bus lanes are present in the network to account for unequal mean speeds between different bus lanes.

Data taking from multiwire chambers and hodoscopes at IHEP physical setups

The LE-73 and LE-78 modules of MISS system designed for readout and recording of signals from multiwire chambers and hodoscopes are described. The use of an Altera FPGA provides a means for producing different modifications of the modules and adapting their operation to specific requirements of experimental setups. Owing to the availability of a high-speed internal memory, it is possible to design time-to-digital converters with a “common stop” and a 5-ns step and to store data in an internal FIFO memory.

LF 안테나 구동기의 디지털 블록 설계

PE(Passive Entry)는 자동차 운전자가 스마트 키를 직접 사용하지 않고 차량의 문을 열거나 닫는 자동차 기술이다. PG(Passive Go)는 운전자가 스마트 키를 갖고 차량 내에 있을 때 시동을 걸거나 끄는 기술이다. 이러한 2가지 기능을 합쳐서 PEG라 부른다. PEG의 핵심 기술 중의 하나인 LF(Low Frequency) 안테나 구동기는 명령을 처리하는 디지털 블록과 sine 파를 발생시키는 아날로그 블록으로 구성되어 있다. LF 안테나 구동기의 디지털 블록은 MCU(혹은 ECU)로부터 명령을 받아서 요청된 명령을 수행하며, 내부의 FIFO 블록에 안테나 구동 관련 명령 및 데이터를 저장한다. FIFO에서 명령을 읽어내 이에 대응하는 조치를 취하며 변조된 LF 데이터를 아날로그 블록에 전달하면 아날로그 블록은 sine 파를 생성하여 안테나를 통해 외부로 전달한다. 설계된 LF 안테나 구동기용 디지털 블록은 기존의 제품과 비교하여 더 빠른 속도로 LF 데이터 전송을 수행할 수 있다. 이의 응용 분야는 자동차용 PEG 및 건물의 출입문 개폐에 활용이 가능하다. PE(Passive Entry) is an automotive technology which allows a driver to lock and unlock door of vehicle without using smart key buttons personally. PG(Pssive Go) is an automotive technology which offers the ability to start and stop the engine when there is a driver in vehicle with smart key. When these two functions are unified, we call it PEG(Passive Entry/Go). LF(Low Frequency) antenna driver which is one of core technologies in PEG is composed of a digital part which processes commands and an analog part which generates sine waveform. The digital part of antenna driver receives commands from MCU(or ECU), and processes requested commands by MCU, and stores antenna-related driver commands and data on an internal FIFO block. The digital part takes corresponding actions for commands read from FIFO and then transfers modulated LF data to analog part. The analog part generates sine waveform and transmits outside through antenna. The designed digital part for LF antenna driver can acomplish faster LF data transmission than that of conventional product. LF antenna driver can be applicable to the areas such as PEG for automotive and gate opening and closing of building.

An adaptable fast and compact DAQ for the luminosity measurement at HERA II

A new data acquisition (DAQ) system for the H1 Luminosity measurement at HERA II has been commissioned in 2002 in parallel with the machine; aiming at 1% precision measurement on each of the 186 colliding bunches in less than 1 min, it is based on a commercial mezzanine processing card mounted on a VME station, reading custom-designed analog-to-digital converter (ADC) and time-to-digital converter (TDC) VME cards via a dedicated bus. The protocol on this 20-MHz data bus is implemented on a field-programmable gate array (FPGA), which also performs the triggering for two acquisition modes (triggered and by train), the synchronization of the digitization boards and the formatting of the data in an internal FIFO. The data are then fetched and histogrammed by a dedicated PowerPC processor. The online analysis of the distributions takes place on the VME station. Maximum histogramming rates of 0.5 MHz have been reached in the train mode (three channels readout) and about 110 kHz in the triggered mode (26 channels readout).

An integrated high performance Fastbus slave interface

Abstract A high performance Fastbus slave interface ASIC is presented. The Fastbus slave integrated circuit (FASIC) is a programmable device, enabling its direct use in many different applications. The FASIC acts as an interface between Fastbus and a “standard” processor/memory bus. It can work stand-alone or together with a microprocessor. A set of address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/s to Fastbus can be obtained using an internal FIFO buffer in the FASIC.