The growing complexity of Multiprocessor Systems on Chips (MPSoCs) is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. The effectiveness of this approach largely depends on the availability of a design methodology. With technology scaling, as the geometries of the transistors reach the physical limits of operation, another important design challenge of SoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The interconnect will be susceptible to various noise sources such as cross-talk, coupling noise, process variations, etc.. Designing systems under such uncertain conditions becomes a challenge. Therefore, the goal is to solve some of the most important and time-intensive problems encountered during NOC design that can be solved with a Fault-tolerant Router.. While preserving the throughput, the network load, and the data packet latency of the NOC router.