Intermetal Dielectric Process Research Articles

Integration of Photodefinable Polybenzoxazole as Intermetal Dielectric for GaAs HBT Technology

Photodefinable polybenzoxazole (PBO) has been integrated as intermetal dielectric in GaAs hetero-junction bipolar transistor (HBT) technology. Process module optimization and integration studies were performed and the results and process flow were compared to those of dry-etch polyimide. The photodefinable PBO is shown to allow the intermetal dielectric process flow to be simplified and the number of processes and equipment to be reduced. Results show that PBO has more planarity than polyimide, when coated on GaAs HBT wafers, which typically have significant topography. The photolithography coat, expose, and develop processes were optimized to obtain the desired dielectric thickness and the required via dimension and sidewall profile, in addition the removal of the PBO from the die street. The PBO thermal curing process was performed at 300oC, while plasma ashing was performed to remove any PBO residue from the bottom of the vias. These results show that the photodefinable PBO film is compatible with, is suitable for, and can be integrated as intermetal dielectric in GaAs HBT technology.

Integration of Photodefinable Polybenzoxazole as Intermetal Dielectric for GaAs HBT Technology

Polybenzoxazole (PBO) is a polymer dielectric that has excellent mechanical, physical, and electrical characteristics and that is used for various semiconductor thin film applications. The PBO has low dielectric constant, and has good thermal stability and thermo-oxidative resistance. Furthermore, the PBO material can be applied by spin-coating and can be cured at temperature of <300oC, which is significantly lower than many other spin-on dielectric materials. These characteristics make PBO suitable for use in many semiconductor technologies and applications that require the processing temperatures not to exceed 300oC, such as GaAs hetero-junction bipolar transistor (HBT) technology. The PBO material is easily processed, and can be made photodefinable by adding photoactive compounds, and therefore be patterned on semiconductor wafers. By using a photodefinable PBO dielectric material, there will not be any need to perform patterning by dry-etch process steps that are typically performed in GaAs technologies.In this study, photodefinable PBO has been integrated as intermetal dielectric in GaAs HBT technology. Process module optimization and integration studies were performed and the PBO results and process flow were compared to those of dry-etch polyimide, which is typically used as intermetal dielectric in GaAs technology. The photodefinable PBO is shown to allow the intermetal dielectric process flow to be simplified and the number of processes and equipments to be reduced. Results show that PBO has more planarity than polyimide, when coated on GaAs HBT wafers, which typically have significant topography. The PBO photolithography coat, expose, and develop processes were optimized in order to obtain the desired dielectric thickness and the required via dimension and sidewall profile, in addition to removing the PBO from the die street. The PBO thermal curing process was performed at 300oC, while ashing was performed to remove any PBO residue in the vias and streets. Figure 1 shows the FIB/SEM images of GaAs wafer after deposition of Metal 1 and coated with photodefinable, after via expose and develop, after cure, and after ash. Figure 2 shows the GaAs HBT wafer with (a) dry-etch polyimide and (b) photodefinable PBO used as intermetal dielectric. These results show that the photodefinable PBO film is compatible with, is suitable for, and can be integrated as intermetal dielectric in GaAs HBT technology.

Combining neural networks and genetic algorithms for optimising the parameter design of the inter-metal dielectric process

An inter-metal dielectric (IMD) is deposited between metal layers to provide isolation capability to a device and separate the different metal layers that are unnecessary in the conduction of electricity. Owing to the complicated input/response relationships of the IMD process, the void problem results in electric leakage and causes wafer scraping. In the current study, we combined neural networks, genetic algorithms (GAs) and the desirability function in order to optimise the parameter settings of the IMD process. Initially, a backpropagation (BP) neural network was developed to map the complex non-linear relationship between the process parameters and the corresponding responses. Moreover, the desirability function and GAs were employed to obtain the optimum operating parameters in respect to each response. The implementation of the proposed approach was carried out in a semiconductor manufacturing company in Taiwan, and the results illustrate the practicability of the proposed approach.

Application of Six Sigma Methodology to Optimize the Performance of the Inter-Metal Dielectric Process

As semiconductor device density increases, integrated circuits generally involve more levels of metallization. In multilevel interconnected metallization schemes, an inter-metal dielectric (IMD) is deposited between metal layers. The basic advantage of this dielectric layer is that it provides good step coverage to help smooth the topology, making it free of pinholes and allowing it to act as a good insulator. The key problem in the IMD layer is the occurrence of voids which may cause electric leakage and later result in yield loss. The occurrence of these voids may be avoided by ensuring an excellent gap-fill capacity. Taking this into consideration, improving the gap-fill capacity is one of the critical issues for the IMD layer. In addition, the quantity of fluorine and the value of voltage ramping to dielectrics breakdown (VRDB) also affect the quality of the IMD layer. The gap-fill capacity, VRDB, and the quantity of fluorine are important quality characteristics for the optimization of the performance of the IMD layer. Due to the complicated inputs/responses relation, it is difficult for the output of the IMD process to reach the desired target. To resolve this problem, this study employs the Six Sigma methodology to reduce the defect in the IMD layer. A case study of a semiconductor manufacturing foundry in Taiwan is illustrated to show the practicability of the Six Sigma methodology.

Reduction of Plasma Process Induced Damage during HDP IMD Deposition

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH unbiased liner deposition before conventional deposition.

Intermetal dielectric process using spin-on glass for ferroelectric memory devices having SrBi2Ta2O9 capacitors

The degradation behavior of integrated Pt/SrBi2Ta2O9/Pt capacitors caused by hydrogen impregnation during the spin-on glass (SOG)-based intermetal dielectric (IMD) process was investigated. SOG was tested as an IMD since it offers better planarity for multilevel metallization processes compared to other SiO2 deposition methods. It was found that the SOG itself does not degrade the ferroelectric performance. Deposition of an under-layer of SiOxNy by plasma-enhanced chemical vapor deposition (PECVD) using SiH4 + N2O + N2 source gases and a SiO2?x capping layer by another PECVD process using SiH4 + N2O source gases produced hydrogen as a reaction by-product. The hydrogen diffused into the SBT layer and degraded the ferroelectric performance during subsequent annealing cycles. A very thin (10 nm) Al2O3 layer grown by atomic layer deposition before the IMD process successfully blocked the impregnation of the hydrogen. Therefore, excellent ferroelectric performance of the SBT capacitors were maintained after the multilevel metallization process as well as passivation. The adoption of SOG in the IMD process greatly improved the surface flatness of the wafer resulting in a higher capacitor yield with very good uniformity in ferroelectric properties over the 8-in.-diameter wafer.

Case histories with sinterhardening low alloy steel powders: E. Akpan, L.G. Roy (Reliance Electric, Weaverville, North Carolina, USA).

The choice of a reactor concept is vital for the success of a research project in plasma-enhanced chemical vapour deposition (PECVD). Two reactor designs are introduced. The so-called remote PECVD (RPECVD) design is characterized by the separation of the plasma from the reaction zone. The moving electrode (ME) concept incorporates a paralle plate reactor with adjustable electrode spacing.Examples are presented to demonstrate applications of the two concepts. Evaluation of a new precursor for Si-X (X = C, Nx, O2, etc.) films is accomplished with RPECVD. RPECVD is also suitable for the treatment of sensitive substates (III–V) semiconductors, plastics). In turn, ME-PECVD should be destined for purposes where two or more process steps have to be combined. An example is proposed with a novel intermetal dielectric process.

New flexible reactor design for R&amp;D PECVD deposition systems

Abstract The choice of a reactor concept is vital for the success of a research project in plasma-enhanced chemical vapour deposition (PECVD). Two reactor designs are introduced. The so-called remote PECVD (RPECVD) design is characterized by the separation of the plasma from the reaction zone. The moving electrode (ME) concept incorporates a paralle plate reactor with adjustable electrode spacing. Examples are presented to demonstrate applications of the two concepts. Evaluation of a new precursor for Si-X (X = C, N x , O 2 , etc.) films is accomplished with RPECVD. RPECVD is also suitable for the treatment of sensitive substates (III–V) semiconductors, plastics). In turn, ME-PECVD should be destined for purposes where two or more process steps have to be combined. An example is proposed with a novel intermetal dielectric process.