Inter-metal Dielectric Layer Research Articles

Performance Analysis of Bump in Tapered TSV: Impact on Crosstalk and Power Loss

This study addresses the first feasible, and comprehensive approach to demonstrate a compact resistance-inductance-capacitance-conductance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLCG</i> ) model for a multi-walled carbon nanotube bundle (MWB) and multilayered graphene nanoribbon (MLGNR) based tapered through silicon via ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> -TSV) along with the different shaped bumps. The physical structures of bumps accurately considered the effect of the high frequency resistive impact and the inter-metal dielectric (IMD) layer. A mathematical framework has been designed for the parasitics of the cylindrical, barrel, hourglass and the tapered bump structures. The bump and via parasitics have been computed by utilizing the current continuity expression, partial inductance method, splitting infinitesimally thin slices of bump and triangular arrangement of tube assemblage. In order to validate the proposed model, the EM simulation is performed and compared against the analytical results. A remarkable consistency of the analytical and EM simulation-based results supports the proposed model accuracy. Furthermore, when compared to the MWB based structures, the MLGNR -based tapered TSV shows a substantial improvement in power loss and crosstalk. Furthermore, regardless of via height, the TSV with tapered bump structure reduces the overall crosstalk induced delay by 33.22%, 28.90%, and 21.61%, respectively, when compared to the barrel, cylindrical and the hourglass structure.

Fabrication of a high-speed plasmonic reflection/transmission modulator

The fabrication of a high-speed plasmonic reflection/transmission modulator for operation at λ0 = 1550 nm is presented and described in detail. Front-side ground and signal contacts provide easy electrical probe access to the device, while allowing the transmission of light through the substrate. Modulation is based on enhanced perturbation of the effective refractive index of grating-coupled surface plasmon polaritons propagating along a metal–oxide–semiconductor structure on silicon. Fabrication steps include deposition of a plasmonic metal patch, deposition of Ohmic contacts, deposition of an Au nanograting coupler overlaid by e-beam lithography, and the application of an intermetal dielectric layer with metalized vias and metal electrical contacts. Current–voltage and capacitance–voltage characteristics verify the electrical integrity of the structure.

Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes

High-density interconnects, enabled by advanced CMOS Cu BEOL technologies, lead to closely placed metals layers. High-aspect ratio metal lines require extensive plasma etching processes, which may cause reliability concerns on inter metal dielectric (IMD) layers. This study presents newly proposed test patterns for evaluating the effect of plasma-induced charging effect on the integrity of IMD between closely placed metal lines. Strong correlations between the plasma charging intensities and damages found in IMD layers are found and analyzed comprehensively.

Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS⁻NEM Hybrid Circuits.

Considering the isotropic release process of nanoelectromechanical systems (NEMSs), defining the active region of NEM memory switches is one of the most challenging process technologies for the implementation of monolithic-three-dimensional (M3D) CMOS–NEM hybrid circuits. In this paper, we propose a novel encapsulation method of NEM memory switches. It uses alumina (Al2O3) passivation layers which are fully compatible with the CMOS baseline process. The Al2O3 bottom passivation layer can protect intermetal dielectric (IMD) and metal interconnection layers from the vapor hydrogen fluoride (HF) etching process. Thus, the controllable formation of the cavity for the mechanical movement of NEM devices can be achieved without causing any damage to CMOS baseline circuits as well as metal interconnection lines. As a result, NEM memory switches can be located in any place and metal layer of an M3D CMOS–NEM hybrid chip, which makes circuit design easier and more volume efficient. The feasibility of our proposed method is verified based on experimental results.

Output power enhancement in AlGaN/GaN heterostructure field-effect transistors with multilevel metallization

To improve wafer utilization efficiency and heat dissipation performance, this paper proposes multilevel metallization-structured, lateral-type AlGaN/GaN heterostructure field-effect transistors (HFETs) on a 150 mm Si substrate using photosensitive polyimide (PSPI) as the intermetal dielectric layer. The maximum drain current of the HFETs is 46.3 A, which is 240% higher than that of conventional AlGaN/GaN HFETs with the same die size. Furthermore, the drain current drop of the HFETs under high-bias operation is reduced from 14.07 to 8.09%, as compared to that of conventional HFETs.

Bonding Pad Over Active Structure for Chip Shrinkage of High-Power AlGaN/GaN HFETs

This paper reports a bonding pad over active (BPOA) structure with photosensitive polyimide (PSPI) as the intermetal dielectric layer to reduce the chip size of high-power enhancement-mode AlGaN/GaN heterojunction FETs (HEFTs) on a 150-mm (6-in) Si substrate. The fabricated AlGaN/GaN HFETs with a BPOA structure exhibited a threshold voltage and a maximum current of 0.6 V and 38.6 A, respectively, at $V_{\textrm {GS}}$ of 6 V. The leakage current was $4.3 \times 10^{-5}$ A at 700 V, which was the same value as that of the AlGaN/GaN HFETs without a BPOA structure. The reliability of the AlGaN/GaN HFETs with the BPOA structure during the packaging process was improved by the PSPI layer and a modified bonding pad structure, which endured the stress during the wedge wire bonding and epoxy molding processes.

Development of chip shrink technology for lateral-type GaN based HFETs using SiO2/polyimide dual IMD layers

This study examined chip shrink technology for lateral-type AlGaN/GaN HFETs on 150 mm Si substrates fabricated with a bonding pad above the active area (BPAA) structure. The SiO2/polyimide layers were used as inter metal dielectric (IMD) layers, which yielded a very low leakage current of 0.58 nA/mm2 even at 1 kV and a good adhesion property after O2 plasma treatment. The fabricated AlGaN/GaN HFETs with the BPAA structure exhibited good device characteristics, such as a low leakage current of 7.1 nA at 1 kV and a drain current of 3.6 A at 2 V, which has the same value compared to that of the AlGaN/GaN HFETs without the BPAA structure, even though the BPAA structure reduced the size of chip by 40%. This suggests that the BPAA structure is a promising method for reducing the size and cost of the lateral-type AlGaN/GaN HFETs.

Effect of Intermetal Dielectric Layer On the Interpoly Dielectric Properties of Nonvolatile Memory Devices

This paper describes the influence of water-related species contained in intermetal dielectric layer on the interpoly dielectric properties of nonvolatile memory devices. P-TEOS layer used as an intermetal dielectric enhances degradation of interpoly dielectric of nonvolatile memory devices due to the water-related components contained in the layer.

Reducing Metal-Lifting Defect during Wire Bonding through Device Structure and Process Optimization

This article focuses on the methods of reducing Lifted Metal (LM) defects by optimizing the semiconductor manufacturing process. The LM defect was found to be associated with the insufficient adhesion between metal layers and Inter Metal Dielectric (IMD) together with cracking IMD layers. 5 feasible methods are applied to decrease LM defects. The wire bonding test results show that the incorporation of Tetraethoxysilane (TEOS) layer between Nitrogen Doped Carbide (NDC) and Black Diamond (BD) proves the most useful to decrease Au wire bonding LM defect to 1/39.8 and Cu wire bonding LM defect to 1/9.25. This method to reduce LM defects has passed all the wafer qualification tests, thus it is being used in IC mass production.

CMOS Capacitive Sensors With Sub-$\mu$m Microelectrodes for Biosensing Applications

Miniaturized complementary metal-oxide semiconductor (CMOS) capacitive sensors presented in this work are capable of providing sensitive detection in the sub-nM range for biosensing applications. A convenient post-CMOS fabrication process is proposed to make sub-μm interdigitated microelectrodes covered by inter-metal dielectric layer as the sensing interface. Capacitance change due to the electrode-analyte impedance is detected by the integrated continuous-time sensing circuit. For immunodetection of mouse IgG and anti-mouse IgG enhanced by 25% gold nanoparticles, the produced interface capacitance changes after specific bindings were -4, -7.4, and -17 fF for the 13-, 95-, and 925-fF microelectrode designs, respectively. Detection of the 200-nM neurotransmitter dopamine (DA) showed interface capacitance changes of 0.22,1.46, and 22 fF for the three designs. Based on the measured circuit noise of 14.2 μV/Hz <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup> , the minimum detectable capacitance changes were 0.3, 2.9, and 22.5 aF, equivalent to detectable DA concentrations of 309, 394, and 203 pM, respectively.

A micromachining technology for integrating low-loss GHz RF passives on non-high-resistivity low-cost silicon MCM substrate

A micromachining technology for integrating high-performance radio-frequency (RF) passives on CMOS-grade low-cost silicon substrates is developed. The technology can form a thick solid-state dielectric isolation layer on silicon substrate through high-aspect-ratio trench etch and refill. On the non-high-resistivity but low-loss substrate, two metal layers with an inter-metal dielectric layer are formed for integrating embedded RF components and passive circuits. Using the technology, two types of integrated RF filters are fabricated that are band-pass filter and image-reject filter. The band-pass filter shows measured minimum insertion loss of 3.8 dB and return loss better than 15 dB, while the image-reject filter exhibits steeper band selection and achieves better than −30 dB image rejection. A 50 Ω co-planar waveguide (CPW) on the substrate is also demonstrated, showing low loss and low dispersion over the measured frequency range up to 40 GHz. The developed technology proves a viable solution to implementing silicon-based multi-chip modules (MCM) substrates for RF system-in-package (RF-SiP).

Behaviour of CPW and TFMS lines at high temperature for RF applications in sub-45 nm nodes

Coplanar waveguide (CPW) and thin film microstrip (TFMS) lines integrating porous ultra low- k as inter-metal dielectric layers ( k = 2.5) and copper as metal, are for the first time experimentally measured up to 110 GHz and under different temperature conditions, up to 200 °C. The extracted attenuation and propagation coefficients of those transmission lines are compared to simulations performed with MAGWEL software, a frequency domain 3-D Maxwell solver. Based on the characterization results some guidelines related to interconnect design are presented for future applications.

Application of Six Sigma Methodology to Optimize the Performance of the Inter-Metal Dielectric Process

As semiconductor device density increases, integrated circuits generally involve more levels of metallization. In multilevel interconnected metallization schemes, an inter-metal dielectric (IMD) is deposited between metal layers. The basic advantage of this dielectric layer is that it provides good step coverage to help smooth the topology, making it free of pinholes and allowing it to act as a good insulator. The key problem in the IMD layer is the occurrence of voids which may cause electric leakage and later result in yield loss. The occurrence of these voids may be avoided by ensuring an excellent gap-fill capacity. Taking this into consideration, improving the gap-fill capacity is one of the critical issues for the IMD layer. In addition, the quantity of fluorine and the value of voltage ramping to dielectrics breakdown (VRDB) also affect the quality of the IMD layer. The gap-fill capacity, VRDB, and the quantity of fluorine are important quality characteristics for the optimization of the performance of the IMD layer. Due to the complicated inputs/responses relation, it is difficult for the output of the IMD process to reach the desired target. To resolve this problem, this study employs the Six Sigma methodology to reduce the defect in the IMD layer. A case study of a semiconductor manufacturing foundry in Taiwan is illustrated to show the practicability of the Six Sigma methodology.

Inter-metal inorganic spin-on-glass dielectric layer in 100 nm generation technology

This study investigates inter-metal dielectric (IMD) layer with a perhydro-polysilazane-based inorganic spin-on-glass (PSZ–SOG) dielectric layer in 100 nm node multilevel metallization technology. When the PSZ–SOG film is cured in N 2 ambient, the via resistance is worsened; the via resistance declines as the number of wafers in sequence increases because the SOG film tends to adsorb a large amount of moisture and forms a porous IMD film structure. However, when it is cured in O 2 ambient, optimization by via adhesion degassing can minimize the slot effect and yield good via resistance. In this study, the non-etchback PSZ–SOG process is integrated by using 100 nm multilevel metallization technology without an expensive high density plasma chemical vapor deposition (HDP CVD) oxide process or modification of design rules. After the SOG curing recipe and degassing condition in the via adhesion film deposition have been optimized, the PSZ–SOG exhibits excellent planarization, a dense IMD structure and good via resistance performance that is comparable with that of the traditional HDP CVD oxide process.

The effect of oxygen content on bonding configuration and properties of low- k organosilicate glass dielectric film

Low- k organosilicate glass (SiOC:H) film as inter-metal dielectric (IMD) layer in advanced ultra-large-scale integrated circuits (ULSI) was deposited by plasma-enhanced chemical vapor deposition (PECVD) with trimethylsilane (TMS) and oxygen. The effects of oxygen on the bonding configuration, optical and electrical properties were investigated by adjusting TMS/O 2 gas ratios. The absorbance spectra of Fourier transform infrared (FT-IR) spectroscopy shows that the frequency of the Si–O stretching vibration mode shifted to a lower wave number (red shift) with an increase in the ratio of TMS/O 2. The related elements contented in SiOC:H films calculated from FT-IR spectra coincided with the analysis of Rutherford backscattering spectroscopy. Results of optical and electrical properties indicated that a lower refractive index (RI), a higher strength of breakdown voltage, a lower dielectric constant, and a lower leakage current density were achieved at lower TMS/O 2 gas ratios.

Comparison of Optical Properties in Al- and Cu-BEOL of CMOS Image Sensor Devices

Two-dimensional optical simulation and experiments have been performed to investigate light propagation through a microlens and intermetal dielectric (IMD) layers in an Al and Cu back-end of line (BEOL) onto a Si photodiode, and its effects on the wave power, as well as optical carriers generated by a visible ray in the Si substrate area, i.e., photodiode of complementary metal oxide semiconductor (CMOS) image sensor (CIS) pixel. It is shown that more optical carriers are generated in the Cu-BEOL for the red color due to the use of higher permittivity SiC in the Cu-BEOL to prevent Cu from diffusing into the dielectric material, resulting in higher optical loss in the higher-permittivity dielectric layers. Thus, the optical power density arriving in the Si substrate is higher in the Al-BEOL than in the Cu-BEOL when the wavelength is blue (470 nm) or green (550 nm) in the visible ray spectrum. Therefore, the structure of a Cu-BEOL in a CIS must be optimized for generating more optical carriers through lower-permittivity IMD materials or by reducing the permittivity difference between SiC (or SiN) and IMD materials without deteriorating the capability as a barrier to Cu diffusion.

Structural and electrical studies on fluorinated amorphous carbon films as intermetal dielectric layer in ULSI devices

Fluorinated amorphous carbon (a-C:F) films were deposited on a p-type Si(100) substrate by using an inductively coupled plasma chemical vapor deposition (ICPCVD) system with a mixture of carbon fluoromethane (CF 4) and methane (CH 4) gases. X-ray photoelectron spectroscopy was used to investigate the various bonding species such as –CF–, –CF 2– and –CF 3 bonds present in the film. The concentrations of the C–F 2 and the C–F 3 bonds in a-C:F film increased at the higher CF 4/(CH 4 + CF 4) flow rate ratios of 70% and 75%. Therefore, we can infer that the greater incorporation of fluorine with carbon is associated with higher binding energy, since more energy is required to take out the electron of the core level due to higher electronegativity of fluorine. The C– V characteristics of an as-deposited film show that the film contains either interface trapped charges or bulk traps and that of annealed film have the interface trapped charges rather than the bulk traps. The lowest dielectric constant of as-deposited and annealed a-C:F films are found to be 2.5 and 2.6 for the CF 4/(CH 4 + CF 4) flow rate ratio of 75%, which shows that the greater incorporation of fluorine in the films helps in decreasing the dielectric constant.

Enhancement of moisture resistance of spin-on low- k HSQ films by hot wire generated atomic hydrogen treatment

Spin on hydrogen silsesquioxane (HSQ) is a material with low dielectric constant ( k) and shows potential as intermetal dielectric (IMD) layers for future VLSI circuits. One major challenge in the integration of these films is the moisture uptake with time, which degrades the electrical performance and hence limits their application. In the present work, we show (under accelerated conditions) that the as deposited films absorb moisture significantly which is reflected in the related signatures in the infrared (IR) spectroscopic data. Subsequently there is an increase in the leakage current with a concurrent decrease in the electrical breakdown field. Upon treatment with atomic hydrogen generated by a hot filament ( T F = 1900 °C), drastic reduction in the moisture absorption is observed. Also there is almost a 2 orders of magnitude reduction in the leakage current and no indication of any electrical breakdown within the range of applied field.

3D proximity effect correction based on the simplified electron energy flux model in electron-beam lithography

We have confirmed the adequacy of simplified electron energy flux (SEEF) model which can be used in proximity effect correction (PEC) in electron beam lithography. The SEEF model enables calculation of the backscattering energy in a multiwiring structure by obtaining a transmission and reflection energy flux map. We prepared a substrate which contained three pairs of W-plug layers and inter-metal dielectric (IMD) layers, and obtained parameters for correction. The extracted transmittance and reflectance were 1 and 0 for the dielectrics, and 0 and 1.7 for the W plugs. The backscattering energies calculated by using these parameters corresponded with experimental data under the various conditions. We also extracted the scattering range of incident and reflected electrons in dielectrics. We found that the ranges of the reflected electrons were greater than those of the incident electrons because of a wider spread of angle. PEC based on the SEEF model enabled high CD accuracy even at the end of the W-plug area. We thus confirmed that the SEEF model can accommodate complex effects, such as scattering in a multiwiring structure or the screening effect, by following the electron’s path.

Selective Silicidation of Co Using Silane or Disilane for Anti-Oxidation Barrier Layer in Cu Metallization

Aiming to realize a conductive passivation layer for copper interconnection, the solid-gas reactions of cobalt films with silane and with disilane to form cobalt silicides are experimentally investigated. X-ray photoelectron spectroscopy revealed that cobalt silicides layers of up to 6 nm thickness can be selectively formed in the reaction at 473–673 K within 5 min without detectable silicon deposition on silicon dioxide, a common inter-metal dielectric layer. Rapid thermal oxidation experiments revealed that the silicided cobalt layers had better anti-oxidation performance than untreated cobalt layers, and the effect of silicidation was to suppress copper out-diffusion through the cobalt layers. Because cobalt-based alloys can be selectively electroless-plated on copper, selective silicidation of cobalt layers will be easily incorporated into device processing.