Interlevel Dielectrics Research Articles

(Invited) Innovations to Enable Extension of Cu Interconnects and Shift to Alternative Conductor

Cu/low-k interconnect is facing challenges in its extension beyond 32nm metal pitch and impacting circuit RC delay adversely. The difficulties lie in securing (#1) Cu gap fill capability in scaled via in the dual damascene process flow due to the limited step coverage of PVD Cu seed layer, (#2) Vx-Mx breakdown voltage and TDDB reliability due to scaled spacing and misalignment in lithography, (#3) Electromigration reliability when the barrier/liner is scaled, (#4) Low line resistance due to decreased Cu volume when the barrier/liner scaling is limited, (#5) Low via resistance when the barrier/liner scaling is limited, (#6) low-k dielectrics patterning due to low-k wiggling in scaled metal pitch and insufficient Young modulus of low-k and (#7) Low interconnect parasitic capacitance when thickness of the plasma-induced damage of the intra-layer low-k dielectric becomes significant comparing to the inter-metal spacing per scaling.Because of these difficulties in extension of dual damascene Cu interconnection scheme, various alternative metallization unit processes, materials (conductors and dielectrics) and schemes (alternative to dual damascene) have been investigated. These new processes and materials include (a) those for extension of Cu technology such as hybrid interconnect where wires stay with Cu and vias are pre-filled with alternative conductor or Cu, and (b) those for entire replacement of Cu to other conductors. However, extension of Cu interconnects is the preference in the industry rather than entire replacement to alternative conductors and/or metallization schemes, partly because of poor competitiveness in line resistance of fine lines. In addition, even when fine Cu lines are replaced to alternative conductors such as Co for fine lines, wide power rails need to stay with Cu for the required low line resistance. Cu/Co composite metallization has been investigated to resolve the problem f high line resistance of power rail. Also, Buried Power Rail (BPR) and Back Side Power Distribution Network (BS-BPN) are potential solution which can support replacement of Cu to alternative conductors.In this talk, process candidates which have potential to resolve the difficulties listed in Table 1 and enable extension of Cu interconnection scheme are reviewed Then, the possibility and challenges to shift from Cu to alternative conductors are reviewed.REFERENCES[1] T. Nogami, et;/al., “Advanced BEOL Metallization”, IEEE IITC 2020[2] T. Nogami, et.al., “Technology challenges and enablers to extend Cu metallization to beyond 7 nm node”, IEEE Proc. VLSI Symp. 2019 T2-2[3] B. Briggs, et.al., “Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node”, IEE Proc, IEDM 2017 14.2.1[4] S. Nguyen, et. al., “Robust Low k C-rich SiCN Interlevel Dielectric with Ultrathin Barrier for Novel RC Reduction in BEOL Cu-Low K Interconnects :, IEEE IITC. Proc. 2019[5] K. Motoyama, et. al., “Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and Beyond”, IEEE Proc. IITC 2018 pp40-42[6] P. S. Bhosale, et. al., “Modified ALD TaN Barrier with Ru Liner and Dynamic Cu Reflow for 36nm Pitch Interconnect Integration”, IEEE IITC Proc. 2018, pp 43-45[7] T. Nogami, et al., “Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes”, Tech. Dig. IEDM 8.1, 2015.[8] T. Nogami, et. al., “Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node:, IEEE Proc. VLSI Symp. 2017 T11-5[9] T. Nogami, “Overview of interconnect technology for 7nm node and beyond - New materials and technologies to extend Cu and to enable alternative conductors”, IEEE Proc. EDTM 2019 pp38-40[10] P. S. Bhosale, et. al., VLSI Symp. 2020[11] T. Nogami, et. al., “Cobalt/copper composite interconnects for line resistance reduction in both fine and wide lines”, IEEE Proc. IITC 2017

Effects of Amino Acids on Silicon Oxide for High Silicon Oxide Removal Rate Ceria Slurry

Chemical mechanical polishing (CMP) is a process for flattening a wafer, and its importance is increasing as design rules are shrunk. There are Inter Level Dielectric (ILD), Shallow Trench isolation (STI), and 3D-NAND CMP processes for polishing the oxide surface in the CMP process. In the case of 3D-NAND CMP, a high removal rate (RR) slurry is required because a thick oxide film must be polished in a short time. Generally, ceria or silica slurries are used in oxide CMP. Ceria slurry shows high RR by Ce-O-Si bonding. The slurry includes additives for purpose of dispersion of abrasive, pH adjustment, change of wafer surface properties. Amino acids have various functional groups depending on the pH. Depending on the activity of the functional groups, the amino acid has various effects on the surface of the slurry or silicon oxide. Amino acids were used additive in slurry and some amino acids increased the removal rate. We investigated the effect of some amino acids on the silicon oxide wafers and ceria slurry. The effect of amino acids on the removal rate was analyzed by zeta potential, contact angle and X-ray photoelectron spectroscopy analysis. Our results indicate that some amino acid adsorb on oxide surface and increase the values of absolute zeta potential. Differences in zeta potential values between slurry and wafer surface make high removal rate. Figure 1

Evolution, Revolution, and Technology Scaling—The Impact on ESD and EOS Reliability

In the scaling of semiconductor devices, evolutionary and revolutionary modifications are made in the device dimension, structural changes and dimensions. The effect of MOSFET scaling on electrostatic discharge (ESD) and electrical overstress (EOS) reliability and robustness have both positive and negative implications. In this publication, the evolutionary and revolutionary technology changes on how they influence the ESD and EOS results will be discussed in full detail. The paper will discuss changes in the substrate, wells, isolation, source/drain regions, gate dielectrics, inter-level dielectrics and interconnects.

Communication—Tribology of Retaining Rings in Chemical Mechanical Planarization

Stribeck and Stribeck+ curves helped determine the tribological mechanisms in the ring-slurry-pad interface. Both methods gave consistent results with the lubrication mechanism starting at “boundary lubrication” and transitioning to “mixed lubrication” as pseudo-Sommerfeld numbers increased. COF for PPS rings were higher than PEEK. They were also higher for inter-level dielectric (ILD) processes as compared to copper. Stribeck curves were used to infer wear rate information about the ring, which in conjunction with Stribeck+ curves could help choose process parameters that balanced wafer removal with ring wear. Data cluster shapes were shown to be due to shear and normal force fluctuations.

Exploring the thermal limit of GaN power devices under extreme overload conditions

The performance of normally-off Gallium-Nitride (GaN) High-Electron-Mobility-Transistors (HEMTs) under extended short circuit operation is investigated. A thermal limit is found in the aluminium metallization, where at temperatures around 600°C a protrusion of the gate metal through the Inter-Level Dielectric (ILD) may form, short-circuiting gate and source metallization and thus resulting in a permanently-off failure state. The present work shows how this particular failure mode can be induced by extreme overload operation, and presents a Finite Element (FE) model which agrees with the experimental observations and gives insights in the mechanical stress-state developing in the device. The deeper thermo-mechanical understanding of the degradation mechanism suggests directions in order to improve the device's robustness.

Planarization effect evaluation of acid and alkaline slurries in the copper interconnect process**Project supported by the Special Project Items No. 2 in National Long-Term Technology Development Plan (No. 2009ZX02308), the Doctoral Program Foundation of Xinjiang Normal University Plan (No. XJNUBS1226), the Key Laboratory of Coal Gasification, Ministry of Education, and the Inorganic Chemistry Key Disciplines of Xinjiang Normal University.

We observed and analyzed the acid and HEBUT alkaline of Cu chemical mechanical polishing (CMP) slurry to evaluate their effects. Material analysis has shown that the planarity surfaces and the removal rate of alkaline slurry are better than the acid slurry during metal CMP processes. The global surface roughness and the small-scale surface roughness by 10 × 10 μm2 of copper film polished by the SVTC slurry are 1.127 nm and 2.49 nm. However, it is found that the surface roughnesses of copper films polished by the HEBUT slurry are 0.728 nm and 0.215 nm. All other things being equal, the remaining step heights of copper films polished by the SVTC slurry and HEBUT slurry are respectively 150 nm and 50 nm. At the end of the polishing process, the dishing heights of the HEBUT slurry and the SVTC slurry are approximately both 30 nm, the erosion heights of the HEBUT slurry and the SVTC slurry are approximately both 20 nm. The surface states of the copper film after CMP are tested, and the AFM results of two samples are obviously seen. The surface polished by SVTC slurry shows many spikes. This indicates that the HEBUT alkaline slurry is promising for inter-level dielectric (ILD) applications in ultra large-scale integrated circuits (ULSI) technology.

Quantum cascade laser based monitoring of CF2 radical concentration as a diagnostic tool of dielectric etching plasma processes

Dielectric etching plasma processes for modern interlevel dielectrics become more and more complex by the introduction of new ultra low-k dielectrics. One challenge is the minimization of sidewall damage, while etching ultra low-k porous SiCOH by fluorocarbon plasmas. The optimization of this process requires a deeper understanding of the concentration of the CF2 radical, which acts as precursor in the polymerization of the etch sample surfaces. In an industrial dielectric etching plasma reactor, the CF2 radical was measured in situ using a continuous wave quantum cascade laser (cw-QCL) around 1106.2 cm−1. We measured Doppler-resolved ro-vibrational absorption lines and determined absolute densities using transitions in the ν3 fundamental band of CF2 with the aid of an improved simulation of the line strengths. We found that the CF2 radical concentration during the etching plasma process directly correlates to the layer structure of the etched wafer. Hence, this correlation can serve as a diagnostic tool of dielectric etching plasma processes. Applying QCL based absorption spectroscopy opens up the way for advanced process monitoring and etching controlling in semiconductor manufacturing.

Thermal Stability of Ultralow k Carbon-Bridged Periodic Mesoporous Organosilica Film

Periodic mesoporous organosilica film was prepared via sol-gel and spin-coating methods using a 1, 2-bis (triethoxysilyl) ethane (BTEE) and a poly (ethylene oxide)-poly (propylene oxide)-poly (ethylene oxide) triblock copolymer template (P123). Thermal treatment at 350°C for 1h resulted in the formation of ultralow dielectric constant (k) film with a k value of 1.82, a leakage current density of 1.58×10-9 A/cm2 at 0.5MV/cm, Youngs modulus of 6.45 GPa, and hardness of 0.58 GPa. Further, thermal treatment at higher temperature up to 500°C still achieves an ultralow k value smaller than 2.0, similar leakage current characteristics, and enhanced mechanical properties. These indicate that synthesized PMO film has robust thermal stability, and very good potential for the application of next-generation inter-level dielectrics.

TiN Metal Hard Mask Removal with Selectivity to Tungsten and TiN Liner

Low-pH titanium nitride (TiN) removal formulations utilizing oxidizers other than hydrogen peroxide (H2O2) have been developed with superior TiN selectivity toward W and the inter-level dielectric (ILD) films. One critical challenge is protecting the TiN barrier layer between the W and dielectric layer, which is often exposed during the TiN metal hard mask (MHM) removal step. This study focused on developing and optimizing formulations with TiN MHM etch rates ≥ 100 Å/min at temperatures ≤ 60oC, with compatibility toward W, ILD films, and the TiN liner. The galvanic corrosion was tailored to protect the TiN liner in the presence of W. A simple yet novel patterned wafer test vehicle was developed to facilitate this work, enabling the investigation of the chemical impact at the W/TiN liner interface.

Poly(benzoxazole-amide-imide) copolymers for interlevel dielectrics: interchain hydrogen bonding, molecular arrangement and properties

A series of novel random poly(benzoxazole-amide-imide) copolymers were synthesized via the poly(amic acid)s from the reaction of 5-amino-2-(4-aminophenyl)benzoxazole (BOA) and 4-amino-N-(4-aminophenyl)benzamide (DABA) with 3,3′,4,4′-biphenyltetracarboxylic dianhydride (BPDA). The corresponding homopolyimides were also prepared for comparison. The chemical composition, interchain hydrogen bonding and molecular arrangement of the copolyimides in solid films were investigated by attenuated total reflectance Fourier transform infrared (ATR-FTIR) spectroscopy, computation techniques and wide angle X-ray diffraction (WAXD). The results indicated that the interchain hydrogen bonds were most likely formed between the amide oxygen atoms and -N-H bands. And the ordered chain packing structures of copolyimide films were completely different from those of the homopolyimide films probably due to the directional interchain hydrogen bonding interactions. The properties of the copolyimides were also well-characterized by tensile tests, dynamic mechanical analysis (DMA), thermal gravimetric analysis (TGA) along with water absorption, solubility and peel tests. All of the obtained copolyimide films exhibited high tensile strength (321 ~ 332 MPa) and modulus (6.76 ~ 8.03 GPa) without any stretching. Moreover, the glass transition temperatures (Tgs) and 5 % weight-loss temperatures of the copolyimides in nitrogen were above 322 and 560 °C, respectively. Additionally, the copolyimide films also exhibited low water absorption, excellent chemical resistance and good adhesion properties suitable for interlevel dielectrics in microelectronics.

Selective High-Throughput TiN Etching Methods

Titanium nitride (TiN) is widely used as a hard mask film protecting the inter-level dielectric (ILD) before metal or plating seed layer deposition steps. It is common practice to use a wet etch in order to remove residues formed during the ILD dry-etch step, and at the same time to remove some or all of the exposed TiN. From its thermochemical properties, it might be predicted that wet etching of TiN should be easy, since it is quite unstable with respect to both plain and oxidative hydrolysis. For example, in acidic solutions at 25°C [1, :

Low-Shrinkage Spin-On Glass for Low Parasitic Capacitance Gap-Filling Process in Advanced Memory Devices

A new low-dielectric-constant spin-on glass (SOG) with a k value of 2.4 has been developed for a gap-filling process in advanced memory devices. The low-shrinkage characteristic of the SOG during thermal curing provides capabilities of gap filling and planarizing as high as those of conventional reflowable SOGs. The low-shrinkage SOG has thermal stability up to 800 °C and chemical stability against diluted hydrofluoric acid, sulfuric acid–hydrogen peroxide, and amine-based solutions, which makes it possible to be used as an interlevel dielectric of memory devices. Tungsten and aluminum interconnects fabricated using the low-shrinkage SOG showed a parasitic capacitance 30% lower than those fabricated using silicon dioxide and a sufficiently long line-to-line dielectric breakdown lifetime. Taking advantage of the high chemical stability of the SOG, an all-wet damageless via-formation process using an amine-based photoresist stripper has been developed. By using the process, the low-shrinkage SOG can be applied to multilevel metallization.

Nonlinear Sequential Bayesian Analysis-Based Decision Making for End-Point Detection of Chemical Mechanical Planarization (CMP) Processes

Chemical mechanical planarization (CMP) process has been widely used in the semiconductor manufacturing industry for realizing highly polished (surface roughness Ra ~1 nm ) and planar [WIWNU ~ 1%, thickness variation standard deviation ~3 nm] surfaces of an in-process wafer. In CMP, accurate and timely decisions for end-point detection (EPD) are extremely important to enable the process to effectively respond to demand variations and disruptions. In this paper, we apply nonlinear sequential Bayesian analysis and decision theory to establish a quantitative relationship that connects the features (inputs) extracted from on-line wireless vibration sensor signals with the process performance measures, such as material removal (outputs) for EPD in copper CMP process. A case study with actual CMP data is provided to demonstrate the effectiveness of the present approach. Note to practitioners. The semiconductor industry widely uses CMP process for realizing highly polished planar surfaces on inter-level dielectrics and metallic interconnects in the fabrication of integrated circuits. Accurate and timely detection of the end-point (EPD) of the CMP process is critical to prevent over-polishing or under-polishing of wafer surfaces, and thus meet the wafer yield requirements under growing demands on wafer density and performance. An EPD system uses information from in-process sensors and/or inspection instruments to facilitate decisions on when to stop the polishing process, and adjust process settings for optimal performance. However, the issue of developing cost-effective sensors, and addressing the uncertainty in the sensor information remains a challenge. We have developed an EPD system based on deriving and sequentially updating a cost-function using the uncertain information from wireless MEMS vibration sensors mounted on a CMP apparatus. Decisions on EPD are made based on optimizing the updated cost function at every time-step. Our experimental investigations suggest that the sensor information can be effectively used for implementing EPD, and it can minimize the costs of over-polishing and under-polishing of wafers during CMP process. As part of future work, we are investigating the robustness of the EPD system to different forms of uncertainty in the sensor information, and much wider configurations of sensors and CMP setups.

ILD CMP with Silica Abrasive Particles: Interfacial Removal Kinetics and Effect of Pad Surface Textures

The removal mechanism for interlevel dielectric (ILD) chemical mechanical polishing (CMP) with fumed silica abrasive slurry was studied by measuring silicon dioxide wafer removal rates as a function of abrasive concentration and pH and also by examining the surface charges of the abrasive particles at different pH’s. The interfacial removal kinetics indicates that the wafer removal rate is consistent with a first-order reaction and is proportional to the concentration of surface silanolates on the abrasive particles. The actual removal is proposed to be achieved by a direct nucleophillic attack of the silica particle silanolates on the wafer Si–O bond. Pad surface texture provides the means to transport the slurry to the contact zone and the effective concentration of abrasive particles doing actual removal is greatly influenced by the pad surface macrotexture by grooving design and the microtexture by conditioning. The observed correlation between the pad surface parameters that are used to characterize the pad microtexture and the removal rate highlights the importance of the pad surface texture to ILD CMP.

Influence of the additives argon, O 2, C 4F 8, H 2, N 2 and CO on plasma conditions and process results during the etch of SiCOH in CF 4 plasma

Reactive ion etch processes for modern interlevel dielectrics become more and more complex, especially for further scaling of interconnect dimensions. The materials will be damaged within such processes with the result of an increase in their dielectric constants. The capability of selected additives to minimize the low- k sidewall damage during reactive ion etching (RIE) of SiCOH materials in fluorocarbon plasmas was shown in different works in the past. Most of the investigated additive gases alter the fluorine to carbon ratio as well as the dissociation of the parent gas inside the etch plasma. The result is a changed etch rate, a modified polymerization behavior and other characteristics of the process induced SiCOH damage. Heavy inert ions like argon will be accelerated to the sample surface in the cathode dark space and enhance therewith the sputter yield on the SiCOH network [1]. In this paper the additives Ar, O 2, C 4F 8, H 2, N 2 and CO were added to a conventional CF 4 etch plasma. We try to provoke different changes in the plasma conditions and therewith in the process results. Contact angle measurements, spectroscopic ellipsometry, Hg-probe analysis, FTIR measurements and SEM cross-sections were used to overview the additive induced modifications. To understand the influences of the additives gases more exactly, changes in the physical and chemical plasma behavior must be analyzed. Therefore quadrupole mass spectrometry (QMS) and quantum cascade laser absorption spectroscopy (QCLAS) were used.

A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology

In this paper, a simple and nondestructive method of modeling 40-nm interconnects is proposed. Traditional methods based on charge-based capacitance measurement model the interconnects by fitting the capacitance or resistance curves, first by assuming one constant process parameter, such as metal thickness, and then by extracting the metal width, metal spacing, and interlevel dielectric (ILD) thickness from certain test patterns that may therefore result in model inaccuracy while the transmission and scanning electron microscopy methods are both destructive and time consuming. The proposed new methodology directly extracts the metal width based on the metal resistance test structures, and then the metal thickness, metal spacing, and ILD thickness without any presumption. It is also nondestructive and fast, with a model accuracy higher than 95%. Furthermore, with the ensured accuracy of layout parameter extraction, the necessity of an accurate interconnect model in the 40 nm technology and beyond is emphasized.

Photodefinable Polybenzoxazole as Interlevel Dielectric and Buffer Layer for GaAs HBT Technology

Polybenzoxazole (PBO) has been investigated and used as interlevel dielectric and buffer layer for GaAs hetero-junction bipolar transistor (HBT) technology. The polymer film is applied by spin-coating, and is photosensitive and photodefinable. These film characteristics allow the simplification of the process flow and allow the elimination of various steps that are typically used to define the vias, streets, and bonding pads. Additionally, this PBO film can be cured at low temperature (>250oC) and the resulting film has good characteristics against moisture absorption and is stable thermally. Furthermore, the film has good planarity and gapfill characteristics, and has excellent mechanical properties. Results show that GaAs device wafers fabricated with this film as interlevel dielectric has good electrical characteristics. When used as buffer layer, the PBO film is shown to be effective in mechanically protecting the underlying devices and interconnections. The use of photodefinable PBO will result in improvement in device quality and reliability, in addition to in significant reduction in capital and consumable cost, and reduction in cycle time of wafers manufactured. All the above characteristics make this PBO film to be well-suited as interlevel dielectric and buffer layer for and compatible with GaAs HBT technology.

Photodefinable Polybenzoxazole as Interlevel Dielectric and Buffer Layer for GaAs HBT Technology

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Electromigration-induced extrusion failures in Cu/low-k interconnects

Electromigration experiments were conducted to investigate the thresholds required for electromigration-induced extrusion failures in Cu/low-k interconnect structures. Extrusions at the anode were observed after long periods of void growth. Characterization of failure sites was carried out using scanning and transmission electron microscopy, which showed that failures occurred through delamination at the interface between the silicon-nitride-based capping layer diffusion barrier and the underlying Cu, Ta liner, and interlevel dielectric (ILD) materials. This interface is subjected to near tensile (mode I) loading with a mode mixity angle between 4° and 7°, estimated using finite-element-method analysis, as electromigration leads to a compressive stress in the underlying Cu. Comparisons of the fracture toughness for interfaces between the capping layer and individual underlayer materials indicate that the extrusion process initially involves plane-strain crack propagation. As Cu continues to extrude, the crack geometry evolves to become elliptical. An analysis of the critical stress required for extrusions based on these observations leads to a value of approximately 710 MPa, which agrees well with the value determined through estimation of the volume of material extruded and the required stress to accomplish this extrusion. The analysis of the critical stress required for extrusion formation also indicates that sparsely packed, intermediate to wide interconnect lines are most susceptible to electromigration-induced extrusion damage, and that extrusion failures are favored by ILDs with low stiffness (low elastic moduli) and thin liners, both of which are needed in future interconnect systems.

Some Practical Issues of Curvature and Thermal Stress in Realistic Multilevel Metal Interconnect Structures

This paper presents the results of a systematic study of curvature and stress evolution during thermal loading in single- and multilevel interconnect line structures which have been deposited on a much thicker substrate. Effects of line aspect ratio, passivation geometry, and metal density within a metalization level on thermal stress evolution in the lines are addressed. The current analytical stress model enables us to predict that interaction between lines on the same level, i.e., in the lateral direction, is so strong that it cannot be neglected. A two-dimensional (2-D) finite element method has been used to verify the accuracy of the current model, while available experimental data have been compared with theory. In order to capture the exact variation of the thermal stresses at different metalization levels, and to investigate the effect of the upper level line arrangements on the stress states at the lower level, a three-dimensional (3-D) finite element analysis was employed. It can be seen that the interaction between levels in the vertical direction is quite weak when the thickness of the interlevel dielectric (ILD) layer becomes comparable to that of the metal layer.