Interlayer Dielectric Deposition Research Articles

Deposition-temperature-dependent stress of capping oxide and its effect on Pt/Pb(Zr1−xTix)O3/Pt ferroelectric capacitor

Two different interlayer dielectric (ILD) materials, electron cyclotron resonance chemical vapor deposition oxide (ECR-OXIDE) and plasma enhanced chemical vapor deposition TEOS oxide (PE-TEOS), were prepared at 400 and 200 °C respectively, on silicon substrates and Pt/Pb(Zr1−xTix)O3 (PZT)/Pt capacitors. It was found that the ILD deposition temperature is a most important parameter for minimizing the degradation of remnant polarization (Pr) during the ILD deposition. Since the stress of PZT capacitor strongly depends on the ILD deposition temperature, the PZT capacitor with PE-TEOS showed more compressive stress than that with ECR-OXIDE, which results in severe Pr degradation of PZT capacitor with PE-TEOS. This large stress effect of PE-TEOS was confirmed by x-ray diffraction (XRD) patterns in which the d spacing of (111) PZT films with PE-TEOS was much larger than that of PZT films with ECR-OXIDE. Therefore, the low ILD deposition temperature is a key parameter for achieving an ILD integration without any Pr degradation.

The effects of interlayer dielectric deposition and processing on the reliability of n-channel transistors

We report on the effects of interlayer dielectric (ILD) deposition and processing on metal–oxide–silicon field-effect transistor's (MOSFET's) Fowler–Nordheim (FN) stress reliability. The ILD materials examined are plasma-enhanced chemical vapor deposited (PECVD) fluorinated silicon oxide (FSO), PECVD tetra-ethyl- ortho-silicate (TEOS), and spin-on polymer. We used n-MOSFETs with 0.35 μm channel lengths and 90-Å-thick gate oxides as our test vehicles and transistor reliability was assessed using transistor parameter, charge-to-breakdown, and charge pumping measurements. We found out that deposition and processing of the polymer ILD have the least damaging effects on transistor's reliability, whereas deposition and processing of the FSO ILD cause the highest device degradation. We also examined the synergy between damage from ILD deposition and processing and damage from plasma etching by measuring a special test module containing transistors with charging antennae that are sensitive to gate-definition plasma etching. We observed that damage from plasma etching dominates over damage from polymer and TEOS ILD deposition and processing as indicated by the direct correlation between FN reliability and the antenna ratio. However, this was observed not to be the case for damage from FSO ILD deposition and processing which was observed to be as effective as plasma etching damage and to give rise to a “reverse antenna” effect; i.e., the smaller the antenna the less reliable the MOSFET. This is attributed to an interaction which involves plasma charging, fluorine diffusion and defect passivation by fluorine.

The Integration of Interlayer Dielectric Deposition and Chemical Mechanical Polishing

ABSTRACTThis paper addresses an important process issue in tie integration of chemical mechanical polishing (CMP) with interlayer dielectric (ILD) deposition for advanced back end processing. Gap fill between metal lines is achieved by using a dep-etch-dep technique for the tetraethylorthosilicate (TEOS) ILD deposition. The ILD layer is then planarized by CMP. Vias are etched through the ILD and filled with tungsten plugs in a blanket tungsten deposition and tungsten CMP sequence. Delamination has been observed at the interface between the TEOS layers following the blanket tungsten deposition and before or during tungsten CMP. The weak interface between the TEOS layers was found to be the result of residual carbon and fluorine from the tetraflouromethane (CF4) doped etch process. The interface between the TEOS layers was examined using X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). Experiments were carried out to determine if the residue and subsequent delamination could be eliminated by modifying the dep-etch-dep process. An improved process was identified and has been implemented on a 0.5μm CMOS and mixed-mode BiCMOS production line with no subsequent occurrence of interfacial delamination.