Interface Trap Charge Density Research Articles

Effect and Determination of Oxide Trapped Charge and Interface Trapped Charge Density of Threshold Voltage Shift in Irradiated MOSFET by Subthreshold Methodology

This paper presents the effects and determination of oxide and interface trapped charge density of threshold voltage shift in irradiated MOSFET by subthreshold methodology. The designed dimension, channel width per channel length (W/L) is 20 µm/20 µm. The threshold voltage is extracted by a linear extrapolation methodology. The over all threshold voltage shifts are caused by oxide trapped charge and interface trapped charge. The subthreshold methodology determines the interface trapped charge. The 60Co gamma-ray source was used for irradiation to a total dose of 10 kGy. The results showed that the threshold voltage shift is approximately -24 mV/kGy for NMOS and -27 mV/kGy for PMOS. The subthreshold swing shift is approximately 1.2 mV/dec.kGy for NMOS and 0.9 mV/dec.kGy for PMOS. The oxide trapped charge density NOT and interface trapped charge density NIT are found to be increased in NMOS and PMOS respectively. The ratio of ΔNOT/ΔNIT was approximately 2.2 times for NMOS and 2.8 times. Due to the structure, the channel of NMOS is a surface channel whereas the channel of PMOS is a buried channel. Finally, the effect of gamma irradiation on the PMOS was greater than the effect on NMOS observed from the change in threshold voltage and the ratio of ΔNOT/ΔNIT.

Effects of ammonia and oxygen plasma treatment on interface traps in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors

A HfO2/Al2O3/AlN stack deposited in a plasma-enhanced atomic layer deposition system is used as the gate dielectric for GaN metal–insulator–semiconductor structures. Prior to the deposition, in situ remote plasma pretreatments (RPPs) with O2, NH3, and NH3–O2 (in sequence) were carried out. Frequency-dependent capacitance–voltage (C–V) measurements reveal that for all the RPP-treated samples, the interface trap density Dit was significantly reduced compared to the sample without RPP. In particular, the NH3-treated sample exhibits an extremely low Dit of ∼1011 cm−2·eV−1 from EC − 0.31 eV to EC − 0.46 eV. To characterize the interface traps at deeper levels, the transfer pulsed I–V measurement was employed further. In the energy range of EC − ET > 0.54 eV, the interface trap charge density Qit of various samples demonstrates the following order: NH3 RPP < NH3–O2 RPP < O2 RPP < without RPP. By adjusting multiple pulse widths, the Dit derived from the Qit result matches the C–V measurement precisely. Moreover, X-ray photoelectron spectroscopy analysis of the Ga 3d core-level indicates that NH3 RPP facilitates the conversion of Ga2O into GaN at high RF power of 2500 W, whereas O2 RPP mainly oxidizes GaN to relatively stable Ga2O3. Combined with the C–V and pulsed I–V measurements, it is confirmed that a strong positive correlation exists between Ga2O and the interface traps, rather than Ga2O3.

Realizing improved performance of metal-insulator-semiconductor diodes with high-k MgO/SiOx stack

With the development of metal-insulator-semiconductor (MIS) field-effect transistors, the thickness of silicon dioxide (SiO2) must be scaled down; however, it causes a large gate leakage current and a low on/off current ratio. Magnesium oxide (MgO) exhibits a dielectric constant as high as 11.2, which is about three times larger than that (3.9) of SiO2; thus the thickness of MgO can be three times greater than that of SiO2 and significantly reduces the gate leakage current. Nevertheless, a large lattice mismatch (22.5%) exists between MgO and Si materials. In the study, the MgO/SiOx stack dielectrics are employed to suppress the large lattice mismatch and improve the performance of MIS diodes. The MgO/SiOx stack largely reduces the oxygen vacancy of MgO from 75% to 52.3%; also the fixed oxide charge and interface trap charge density are drastically decreased from 1.3 × 1012 and 1.8 × 1013 to 8.2 × 1011 cm−2 and 7.8 × 1012 cm−2eV−1, respectively. Compared to the MIS diodes with a single MgO, the MgO/SiOx stack dielectrics suppress the gate leakage current by about two orders in MIS diodes; hence the rectification ratio is enhanced from 114 to 1032 at ±2V. Band-diagram shows that Fowler-Nordheim tunneling occurs at a high reverse-bias voltage, and the barrier height increases from 0.18 to 0.42 eV in the MIS diodes with single MgO and MgO/SiOx stack dielectrics, respectively. Nevertheless, the MIS diodes operate through a direct tunneling at low reverse-bias voltages.

Impact of band edge energy on interface traps and electrostatics of ultra-thin-body silicon-on-insulator devices

Besides being impacted by quantum confinement effects, the channel electrostatics of ultra-thin-body silicon-on-insulator (SOI) MOS devices, with channel thicknesses less than 10 nm, are also likely to be impacted by interface trap states. In this work, we comprehensively investigated the effect of band edge energy (surface passivation energy) on the band structure of the silicon channel. We propose to utilize this band edge energy (ΔEedge) to study the effect of interface traps on device electrostatics, which is generally used to passivate the channel/oxide interface. First, by using sp3d5s∗ semi-empirical tight-binding methodology with a fully passivated interface (ΔEedge>5 eV) and by including suitable bandgap correction for different device temperatures, the band structure is obtained, which is solved self-consistently with Poisson’s equation to accurately determine the channel electrostatics, without the effect of trap states. Interface trap states are now seen in the band structure through suitably varying the edge energy (−5eV<ΔEedge<5 eV) based on which the interface trap density (Dit) and the interface trap charge density (Qit) are determined. Through incorporating Qit in the boundary condition for solving Poisson’s equation self-consistently with the band structure, channel electrostatics is recomputed to analyze the effect of traps for a wide range of device conditions. Finally, the degradation in the integrated charge density due to interface traps is accurately modeled for different SOI channel thickness and device temperatures.

All region analytical modeling of 2-D transition metal dichalcogenide FET by considering effect of fringing field and region-wise mobility

In this paper, for the first time an analytical all region model of Transition metal dichalcogenide based FET has been developed to represent the current–voltage characteristics of the device in ultra-short channel regime. Starting from Gauss’s law, Poisson’s equation is formulated and short channel subthreshold current model is developed subsequently. In order to include fringing field effect, the gaussian box is considered for top and bottom oxides along with channel. Next, Velocity saturation model is developed by considering mobile charges due to top-bottom gates and region-wise field dependent mobility in the channel utilizing the drift diffusion approach. Both the models are then unified by finding the natural points of transition from one model to other. The intraband source to drain tunneling has also been incorporated to develop generalized 2-D material based FET model. Veracity of the model has been verified with NEGF simulations for different device parameters and excellent congruence is observed. The effect of the interface trap charge density has also been included in the model and its effects on the transfer characteristics are investigated. • Analytical modeling of I-V characteristics for TMD materials applicable for all channel lengths. • Validation of model with atomistic simulator data for Sub 10 nm channel length. • Effects of double gate and fringing field have been included. • Source to drain tunneling has been included to increase model applicability for any 2D materials.

Charge Pumping Technique to Measure Polarization Switching Charges of FeFETs

This study proposes a new method to measure the polarization charge of ferroelectric field-effect transistors (FeFETs) using a pulse generator and source measurement unit (SMU) and exploiting the charge pumping (CP) principle, which is widely followed to measure the interface trap charge density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}_{\text{it}}$ </tex-math></inline-formula> ) of MOSFETs. Although the pulse waveforms applied to the gate electrode were equal to that of conventional polarization charge measurement methods, the response current was measured using the SMU similar to that in CP. As the proposed method measured the average dc current on the well or source/drain terminal, it provided a reliable quantification of polarization charges with low noises even at lower applied voltages. This measurement is possible because the ferroelectric (FE) dipole-induced charge is immovable, similar to an interface charge that is not moved by an interface trap until it recombines with a movable opposite carrier. This method conveniently measured the switching charge even for < 50 ns of rising/falling time of the applied pulse. Moreover, as the read current resolution of the SMU is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ &lt; 5\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> A, the switching charge can be measured with a device area <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ &lt; 1 \boldsymbol {\mu }\text{m}$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Thus, the proposed CP-based method proved to be a highly effective method of polarization charge measurement for three- or four-terminal devices, such as FeFETs, unless the measurement requires the hysteresis curve along with polarization charges.

Impact of unpreventable induced interface trapped charges on HZO based FDSOI NCFET

In this paper, the effect of oxide-semiconductor interface trapped charges on the performance of 22-nm Fully Depleted Silicon on Insulator (FDSOI) Negative Capacitance FET (NCFET) has been systematically investigated. Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) type NCFET with zirconium doped HfO2 (HZO) as the ferroelectric material is considered for this work. The simulation of the underlying Metal-Insulator-Semiconductor (MIS) structure has been carried out in a well-calibrated TCAD environment to extract the gate charge. Which is subsequently used to solve 1D Landau-Khalatnikov (1D-LK) model to find the voltage across ferroelectric capacitor. The presence of trap charges is unavoidable in modern devices, which affects the charge balance equation as well as the performance & reliability of the device. NCFET being one of the potential candidates to be adopted by industry for ultra-low power applications in the future according to the International Roadmap for Devices and Systems (IRDS), investigation of trap charges becomes crucial. Due to its multilayer stacking, the transfer characteristics are analyzed for various ferroelectric thicknesses with exhibition of an intersection point, which is demonstrated for the first time. Simulation of variation of device performance metrics like minimum sub-threshold swing (min. SS), transconductance (gm), off-state drain current (Ioff) & amplification factor (AV) are analyzed and compared for various interface trapped charge densities. It is predicted that the device performance either enhances or degrade depending on the type of trapped charges present.

Post-annealing treatment in improving high dielectric constant MgO-based metal-oxide-semiconductor diodes

Metal-oxide-semiconductor (MOS) diodes with a high dielectric constant magnesium-oxide (MgO) insulating layer were fabricated using a magnetron radio frequency sputtering system. MgO has a high dielectric constant of approximately 11.2, which is three times higher than the dielectric constant (3.9) of silicon dioxide (SiO2), thereby ensuring a three times thicker gate oxide and reducing gate leakage current while maintaining the same capacitance density. Post-annealing treatment was employed on the MgO film to study how annealing treatment affects the electrical characteristics of MOS diodes. It was observed that the post-annealing treatment of MgO effectively diminished the gate leakage current by approximately one order, thereby increasing the rectification ratio from 8.5 × 103 to 6.8 × 104 for the MOS diodes with as-deposited and post-annealed MgO. In contrast to the MOS diodes with as-deposited MgO, the post-annealing treatment of MgO significantly decreased the flatband voltage shift from 7.8 to 1.3 V and reduced the fixed oxide charge density from 1.3 × 1012 to 2.3 × 1011 cm−2; also, the interface trap charge density was suppressed from 1.8 × 1013 to 3.2 × 1012 cm−2 eV−1. Large quantities of fixed oxide charge attracted more electrons accumulated at the Si surface, which decreased the barrier height from 0.85 to 0.81 eV for the MOS diodes with post-annealed and as-deposited MgO. Moreover, x-ray photoelectron spectroscopy showed that the oxide charges were caused by the defects inside MgO, particularly oxygen vacancies. The oxygen vacancies were compensated by the oxygen atoms introduced from the air during the post-annealing treatment.

Effect of high-radiation-dose-induced structural modifications of HfSiO4/n-Si on electrical characteristics

High-k/n-Si structures were formed with HfSiO4 films annealed at the temperature range of RT (room temperature)-900 °C and radiation-induced structural modifications were determined by XRD (X-ray diffraction) and XPS (X-ray photoelectron spectroscopy) techniques in the study. The effect of oxygen-deficient bond contents on the electrical characteristics of HfSiO4 pMOS (n type Metal Oxide Semiconductor) capacitors whose radiation response was investigated in the 0–50 kGy dose range was investigated. While no XRD peak was observed before and after irradiation at RT and 500 °C-HfSiO4/n-Si, crystallization started with irradiation at 900 °C. The dielectric constant of the film was found in the range of 16–23. It was determined that Hf–Hf oxygen-deficient bonds act as negative charge trapping centers, while Hf–Si and Si–Si oxygen-defective bonds act as positive charge trapping centers. The direction of the C–V (Capacitance-Voltage) curve changed continuously with increasing radiation dose. The change in the interface trap charge density was found to be higher than the change in the oxide trap charge density for all doses in RT-HfSiO4 pMOS capacitor and for 1 kGy at 500 °C-HfSiO4 pMOS capacitor. Oxygen defective bond content and Hf-O-Si/Si–O–Si ratios were sufficient to establish a link between structural analyses and electrical characteristics at some doses. In some cases, the frequency-dependent charges had a more dominant effect on the radiation response of the device compared to the oxide trap charges.

Interfacial charge analysis and temperature sensitivity of germanium source vertical tunnel FET with delta-doped layer

The influence of interface trap charges (ITCs) and reliability of the Germanium source vertical tunnel field effect transistor with delta-doped layer (GSDD vTFET) is investigated in this paper. The analysis is carried out on the GSDD vTFET by evaluating the analog/RF performances under the consideration of donor and acceptor ITCs and temperature variations. The presence of interface trap charges at the silicon channel/gate oxide interface changes the flat-band voltage, affecting the analog and RF performances of the GSDD vTFET. The study is carried out at distinctive donor and acceptor interface trap charges. The findings indicate that as the interface trap charge densities increases, the device's output changes drastically. The off-state current of the GSDD vTFET deteriorates significantly from an order of 10−14 A to 10−8 A in the presence of positive ITC of 1012/cm2. The temperature variations over a wide range shows that OFF-state current as well as subthreshold region gets deteriorated due to dominance of Shockley–Read–Hall effect and the superthreshold region is less affected owing to dependence of band-to-band tunneling. The results reveal that when the temperature is raised from 200 K to 400 K, the ION/IOFF current ratio degrades tremendously from ~1014 to ~108 in the existence of donor ITC. It is also observed that the GSDD vTFET is less susceptible to acceptor interface trap charge in comparison with donor ITC in a temperature sensitive environment. Quantum correction (QC) of GSDD vTFET with ITC shows the same type of variations as the condition without considering QC.

Low Interface Trapped Charge Density for AlO/β-GaO (001) Metal-Insulator-Semiconductor Capacitor

In this letter, high-performance Al2O3/β-Ga2O3 (001) metal-insulator-semiconductor (MIS) capacitor has been demonstrated. The capacitance-voltage (C.V) curves of the Al2O3/β-Ga2O3 (001) MIS capacitor remain stable under different measurement frequencies. The leakage current density is lower than 2.0 × 10-8 A/cm2 when the gate voltage is in the range of –5 13 V. The fixed charge and trapped charge densities in Al2O3 film are 4.4 × 1012 and 6.0 × 1011 cm-2, respectively. Average and minimum interface trapped charge density (Dit) for Al2O3/β-Ga2O3 (001) interface has been extracted to be as low as 3.3 × 1011 and 2.3 × 1011 cm-2 eV-1 via the Terman method, respectively. The low Dit is probably attributed to the modification of vacancy defects and the introduction of hydroxyl groups at the Al2O3/β-Ga2O3 (001) interface after piranha solution pretreatment for β-Ga2O3.

Damage effect of hafnium oxide gate dielectric based metal–oxide–semiconductor structure under gamma-ray irradiation

The radiation response of HfO2 films on a silicon substrate under gamma rays is studied in this article. HfO2 films with the thickness of 12.8 and 4.3 nm are prepared on a p-type silicon substrate by using the atomic layer deposition method, and the HfO2/Si MOS structure is irradiated under gamma rays with the total dose of 1.2/2.5/4 Mrad. The generation, transportation, and trapping characteristics of radiation induced charges are studied by using electronic, physical, and chemical methods. First, radiation induced oxide and interface trapped charge densities are found to be up to 1012 cm−2, and oxygen vacancies in HfO2 and Hf–Si metallic bonds at the HfO2/Si interface are dominant defects in the HfO2/Si system. Second, the leakage current through HfO2 increases with the increase in the radiation total dose and the crystallinity also increases after a large total dose of irradiation. Third, the valence band offset between HfO2 and Si is found to decrease slightly after irradiation. From the results, we can see that HfO2 is radiation resistant from the aspect of charge trapping even under a very large total dose of radiation, but the radiation induced leakage current and crystal structure change in the HfO2 film cannot be ignored. This provides a reference for microelectronic devices working in the space environment.

Charge-Plasma Based Cylindrical Nanowire FET for Low-Noise and High Sensing

A dopingless Cylindrical Nanowire Field Effect Transistor is proposed by implementing the charge plasma technique. The charge plasma technique helped in the necessary doping of the source/drain regions. The significance of using charge plasma based Nanowire FET for low-noise and higher sensing applications is investigated by analyzing the linearity parameters and compared with the Junctionless Nanowire FET. The proposed device is optimized as per the practical conditions by taking the interface trap charges into account. The interface trap charges are considered at the gate oxide-channel interface. The variation of interface trap charge (ITCs) density varies the device performance depending on the ITC polarity. The presence of ITCs can enhance device performance by tweaking the ITCs amplitude with positive polarity. The work function of the source/drain metal for the charge plasma technique is varied to get an optimized value. The higher value of source/drain metal degrades the device performance. The voltage interception point of the proposed device is greater than 5 times the actual value of the input signal. The drain current decreases drastically with the increase of source/drain work function independent of the gate bias.

A generalized EKV charge-based MOSFET model including oxide and interface traps

This paper presents a generalized EKV charge-based MOSFET model that includes the effects of trapped charges in the oxide bulk and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions for the mobile charge density and the drain current. These simple formulations demonstrate the effects of charge trapping on MOSFET characteristics and crucial device parameters. The proposed charge-based analytical model, including the effect of velocity saturation, is successfully validated through measurements performed on devices from a 28-nm bulk CMOS technology. Ultrahigh total ionizing doses up to 1 Grad(SiO2) are applied to generate oxide-trapped charges and activate passivated interface traps. Despite a small number of parameters, the model is capable of accurately capturing measurement results over a wide range of device operation from weak to strong inversion. Explicit expressions of device parameters also allow for the extraction of the oxide- and interface-trapped charge densities.

Design and Investigation of Split-Gate MoTe2-Based FET as Single Transistor AND Gate Using Nonequilibrium Green’s Function

Failure of metal–oxide–semiconductor field-effect transistor (MOSFET) in the nanometer regime has raised concern for the researchers. Although researchers have provided solutions in the form of tunnel FETs and junctionless transistors but due to their fabrication issues, MOSFET remains as the backbone of the very large-scale integration (VLSI) industry. This work is dedicated to the design and study of the novel split-gate MOSFET made up of transition metal dichalcogenide. The proposed design can help in realizing digital gates because the device is used as a single transistor AND gate in this work. The device is analyzed for different conditions like the variation in work function, variation in gate length, variation in spacer oxide, and effect of interface trap charge (ITC) density. Nonequilibrium Green’s Function is used as an elemental model of the transistor to include quantum effects for scaled-down dimensions. This work shows that the proposed device results in a noticeable flow of current only when both the gate terminals are at higher potential, that is, at state “11.” The observed linearity is good enough for the efficient working of the device. Hence, the device can be utilized as AND gate with a lesser area and power dissipation.

Investigation of interface trap charges and temperature variation in heterostacked-TFET

This paper analyzes the reliability issues of the Heterostacked-TFET (HS-TFET) in detail. The investigation of the device reliability is carried out by examining the effect of interface trap charges (ITCs) and the temperature affectability of the HS-TFET on various analog parameters and RF FOMs. The analysis is performed at different interface trap charge densities and polarities. The presence of interface traps at the stackedsource/channel junction and the oxide/silicon interface alters the performance of the device significantly. A positive trap charge density of 3 × 1013 cm−2 degrades the current switching ratio tremendously from an order of 1010–104. The off-state current of the device deteriorates excessively at high temperatures. However, the results establish that the HS-TFET is insusceptible to the acceptor interface trap charge as compared to the donor interface trap charge for temperature variation. A high-k gate dielectric of Aluminum oxide (Al2O3) is considered and compared with Hafnium oxide (HfO2) and it is found that Al2O3 gate oxide has a better immunity to the ITC variation.

Hexene passivation on a p-type Zn-doped InGaAs surface

Indium gallium arsenide (InGaAs) is a promising candidate for high-performance complementary metal-oxide-semiconductor (CMOS) channel materials. In this study, self-assembled monolayer passivation was performed on the surface of p-type Zn-doped InGaAs to improve the semiconductor/dielectric interfacial electrical properties. In particular, the oxidation behavior and surface state change that occurred with hexene passivation were analyzed. A relatively thin oxide was formed on the hexene-passivated InGaAs surface and compared to the unpassivated surface after exposure to air over time. It was observed that oxidation was effectively suppressed for all the In, Ga, and As elements. It is considered from the relationship between the oxidation time and the oxide thickness change that the initial oxidation surface reaction is hindered by hexene passivation. In addition, the depletion depth was reduced from 28.2 to 24.4 nm and the interface trapped charge density of InGaAs MOS capacitor was decreased from 4.29 × 1013 to 2.24 × 1013 cm−2eV−1 after hexene passivation. The improvement in the interfacial electrical performance of the MOS capacitor may result from the suppressed oxidation caused by the passivation with hexene on the InGaAs surface.

Experimental optimization of post metal annealing on fully depleted-silicon on insulator tunneling field effect transistor

Many attempts have been made to improve the performance of tunneling field-effect transistors (TFETs). Among these, post metal annealing (PMA) can induce enhanced device performance, but its application to TFETs has not been sufficiently explored. In this study, the temperature, time, atmosphere, and pressure conditions for the PMA of a TFET device are optimized. To evaluate if any loss in performance occurred after PMA, we tested the transistors’ electrical parameters, specifically their subthreshold slopes and low-frequency noises at 10 Hz. Moreover, the interface trap charge density of the TFETs is extracted as a measure to evaluate their performance. As a result, lower temperatures and shorter PMA times are essential compromises, and the performances were improved under H2 and D2-containing atmospheres. Furthermore, the benefit of having high gas pressures during PMA is noted, because as the number of hydrogen/deuterium atoms increases, more traps-removing surface-gas interactions can occur.

Influence of frequency and gamma irradiation on the electrical characteristics of Er2O3, Gd2O3, Yb2O3, and HfO2 MOS-based devices

The unique physical, chemical, and electronic properties of rare earth oxides have been of immense interest to replace SiO2 as a dielectric material in metal–oxide–semiconductor (MOS)-based sensors applications to accurately measure the radiation dosage and increase sensor sensitivities in as diverse applications as space radiation, nuclear physics, medical diagnostics, radiation cancer therapy, and personal dosimetry devices. Hence, the electrical characteristics of oxides prior to and after irradiation of MOS-based devices are needed since they are the backbone of the devices such as MOSFETs and ICs. In addition, an understanding of the behaviour of high-k dielectric oxides in an MOS configuration is necessary since the radiation-induced damage occurs in the bulk oxide film and/or near the oxide–semiconductor interface resulting in creation of lattice defects. Hence, MOS structures with the rare earth oxides of Er2O3, Gd2O3, Yb2O3, and a transition metal oxide of HfO2 were produced by RF magnetron sputtering to determine (a) the structure of the films, (b) dielectric constants, (c) capacitance versus voltage behaviour of Er2O3, Gd2O3, Yb2O3, and HfO2 prior to and after irradiation of the devices in the dose range of 0–76 Gy. The experimental results were analysed with a theoretical framework on the energy band diagram and the radiation effects on the electrical characteristics of the MOS capacitors. The characteristics of the devices were evaluated by using effective oxide charge density ( $$ Q_{\text{EFF}} $$ ), variation in the oxide trapped charge density ( $$ \Delta N_{\text{ox}} $$ ), and interface trapped charge density ( $$ \Delta N_{\text{it}} $$ ). In addition, barrier height ( $$ \phi_{\text{b}} $$ ), image force barrier lowering ( $$ \Delta \phi_{\text{b}} $$ ), acceptor concentration ( $$ N_{\text{a}} $$ ) were calculated before and after irradiation and examined the nature of interface states. The radiation responses of the Er2O3 and HfO2 MOS capacitors did not show a stable behaviour with an increase in radiation dose due to possible neutral electron trap centres. Contrary to expectations, we infer that more negative charges are trapped in Gd2O3-based device than positive charges with an increase in radiation dose. The C–V curves of the Yb2O3 MOS capacitor shifted in the same direction at both 100 kHz and 1 MHz, and as expected, positive charge traps in the structure are more efficient than negative charges. The observed sensitivities of Yb2O3 MOS capacitors are 4–7 times higher than those of SiO2, and the sensitivities of the Yb2O3 MOS capacitors with a total radiation dose of 70 Gy were found to be around 28.08 mV/Gy at both 100 kHZ and 1 MHz frequencies. The Yb2O3 appears to be a promising dielectric candidate for developing a new generation of radiation sensors with an excellent interface quality when compared to rare earth mixed oxides such as silicates, transition metal oxides, and the silicates based on transition metals, Al2O3, and BiFeO3. Our review of the literature suggests that while the radiation damage has been assessed comprehensively based on the C–V characteristics, microstructural characterization of the irradiated films and their interfaces is lacking even though the quality of oxide/Si interface is the most important feature of the devices. The electrical data should be correlated with the inferences from XPS, AFM, TEM, XRD, and other techniques. Further progress requires selection and validation of material properties based on theoretical calculations and predications, utilization of diverse thin film processing and characterization techniques, determining the effect of thickness on the properties of MOS capacitors, a thorough understanding of the interfaces, effect of frequency on the MOS capacitors and the interface characteristics, effect of radiation on the physical, interfacial, and electrical characteristics of MOS capacitors, and preparation and characterization of sensors based on thin films of novel mixed oxides and silicates of different chemistries.

The Study of Deep Level Traps and Their Influence on Current Characteristics of InP/InGaAs Heterostructures

The damage mechanism of proton irradiation in InP/InGaAs heterostructures was studied. The deep level traps were investigated in detail by deep level transient spectroscopy (DLTS), capacitance–voltage (C–V) measurements and SRIM (the stopping and range of ions in matter, Monte Carlo code) simulation for non-irradiated and 3 MeV proton-irradiated samples at a fluence of 5 × 1012 p/cm2. Compared with non-irradiated samples, a new electron trap at EC-0.37 eV was measured by DLTS in post-irradiated samples and was found to be closer to the center of the forbidden band. The trap concentration in bulk, the interface trap charge density and the electron capture cross-section were 4 × 1015 cm−3, 1.8 × 1012 cm−2, and 9.61 × 10−15 cm2, respectively. The deep level trap, acting as a recombination center, resulted in a large recombination current at a lower forward bias and made the forward current increase in InP/InGaAs heterostructures for post-irradiated samples. When the deep level trap parameters were added into the technology computer-aided design (TCAD) simulation tool, the simulation results matched the current–voltage measurements data well, which verifies the validity of the damage mechanism of proton irradiation.