Interface Trap Generation Research Articles

Ultrathin Al2O3 interfacial layer for Hf0.5Zr0.5O2-based ferroelectric field-effect transistors

In this study, the effects of an Al2O3 interfacial layer (IL) on the characteristics of ferroelectric field-effect transistors (FeFETs) with Hf0.5Zr0.5O2 (HZO) gate dielectrics on Si substrates were investigated. FeFETs with HZO gate dielectrics have gained considerable attention owing to their compatibility with modern fabrication processes and scalability. However, during HZO deposition on Si substrates, an ultrathin metal silicate IL with a low dielectric constant is formed in an uncontrolled manner, leading to a significant voltage drop and the generation of interface traps during device operation. To address this issue, an ultrathin Al2O3 IL with a thickness less than 2 nm was introduced between the HZO film and Si substrate via in situ atomic layer deposition. The impact of this IL on a memory window (MW) and endurance characteristics was evaluated by comparing the devices with and without an intentional Al2O3 IL. The obtained results revealed that the Al2O3 IL effectively suppressed the interface trap generation, expanded the MW, and enhanced the transistor endurance characteristics. This described approach can be potentially used for improving the reliability of FeFETs fabricated on Si substrates.

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (-2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.

Impact of low-dose radiation on nitrided lateral 4H-SiC MOSFETs and the related mechanisms

Lateral type n-channel 4H-SiC metal--oxide--semiconductor field effect transistors (MOSFETs), fabricated using a current industrial process, are irradiated with gamma rays at different irradiation doses in this paper to carry out a profound study on the generation mechanism of radiation-induced interface traps and oxide trapped charges. Electrical parameters (e.g., threshold voltage, subthreshold swing and channel mobility) of the device before and after irradiation are investigated, and the influence of the channel orientation ( and ) on the radiation effect is discussed for the first time. A positive threshold voltage shift is observed at very low irradiation doses (< 100 krad (Si)); the threshold voltage then shifts negatively as the dose increases. It is found that the dependence of interface trap generation on the radiation dose is not the same for doses below and above 100 krad. For irradiation doses < 100 krad, the radiation-induced interface traps with relatively high generation speeds dominate the competition with radiation-induced oxide trapped charges, contributing to the positive threshold voltage shift correspondingly. All these results provide additional insight into the radiation-induced charge trapping mechanism in the SiO2/SiC interface.

Fowler–Nordheim Stress-Induced Degradation of Buried-Channel-Array Transistors in DRAM Cell for Cryogenic Memory Applications

The degradation of the fin-type buried-channel-array transistor (BCAT) in dynamic random access memory (DRAM) cell is investigated under Fowler–Nordheim stress at various temperatures, including 77 K. While the increase in the OFF current is dominated by the Shockley–Read–Hall junction leakage, the threshold voltage shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{T}$ </tex-math></inline-formula> ) comprises a positive component due to the interface trap generation and a negative component resulting from the electric field concentration-induced charge trapping into the gate insulator bulk, with respective activation energies of 0.22 and 0.13 eV. Furthermore, based on the consistency between the experimentally decomposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{T}$ </tex-math></inline-formula> components and the simulated ones, it is found that the anode hole injection dominates the degradations of the wordline-active operation and refresh time in cryogenic DRAM.

Influence of Fin and Finger Number on TID Degradation of 16-nm Bulk FinFETs Irradiated to Ultrahigh Doses

This article investigates the fin- and finger-number dependence of the total ionizing dose (TID) degradation in 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs designed with different numbers of fins and fingers are irradiated up to 500 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and then annealed for 24 h at 100 °C. The TID responses of nFinFETs are insensitive to the fin number, as dominated by border and interface trap generation in shallow trench isolation (STI) and/or gate oxide. However, pFinFETs show a visible fin-number dependence with worst tolerance of transistors with the smallest number of fins. The fin number dependence may be related to a larger charge trapping in STI located at the opposite lateral sides of the first and last fins. In addition, both n- and p-FinFETs exhibit an almost TID insensitivity to the finger number. During the design of integrated circuits, the TID tolerance of electronic systems can be enhanced by preferably using transistors with a higher number of fins than fingers.

Negative-Bias-Stress and Total-Ionizing-Dose Effects in Deeply Scaled Ge-GAA Nanowire pFETs

Negative-bias-stress and total-ionizing-dose (TID) effects in deeply scaled Ge-gate-all-around (GAA) nanowire (NW) devices are characterized for different biasing conditions. Negative-bias-stress-induced degradation in Ge GAA device originates primarily from the interface- and border-trap generation. Devices stressed at high gate voltage show rapid initial degradation and quick saturation dominated by interface-trap generation. Radiation-induced OFF-state leakage current in Ge GAA NWs increases with dose due to enhanced band-to-band tunneling (BTBT) caused by charge trapping in the shallow trench isolation (STI).

Unraveling the Dynamics of Charge Trapping and De-Trapping in Ferroelectric FETs

In this work, a comprehensive study of charge trapping and de-trapping dynamics is performed on n-channel ferroelectric field-effect transistors (nFeFETs) and pFeFETs. It is discovered that: 1) the degree of charge trapping depends on the substrate that nFeFETs exhibit significant electron trapping but negligible hole trapping during memory write while pFeFETs exhibit much less electron trapping but significant hole trapping when heavily stressed; 2) due to enhanced electric field in the interlayer and semiconductor, the like initial polarization states (i.e., initialized by a pulse of the same polarity as the write pulse) could exacerbate charge trapping induced by the write pulse; 3) electron trapping is fully recoverable while hole trapping shows a semi-permanent component which involves interface trap generation; and 4) less significant charge trapping in pFeFETs allows immediate read-after-write at normal operating conditions.

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO2-Based Ferroelectric Field Effect Transistor

The endurance of the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based ferroelectric FET (FeFET) is investigated using various program/erase (PG/ER) pulse schemes. The ramp time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ramp</sub> ), which is the time to reach the PG/ER voltage, and the hold time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hold</sub> ), which is the time duration to maintain the PG/ER voltage, are adjusted, and thereafter, their influence on endurance is observed through the memory window, subthreshold slope, and threshold voltage of the FeFET while the FeFET is cycled up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> by a sequence of PG/ER pulses. Both parameters are closely related to depassivating interface traps, and it turns out that a long T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ramp</sub> but short T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hold</sub> are desirable to suppress the interface trap generation in FeFET. The relation between T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ramp</sub> , T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hold</sub> and the interface trap generation is explained by the transient built-in electric field (which is generated by the transiently trapped carrier in the gate oxide when the gate voltage is swept rapidly).

Accurate determination of threshold voltage shift during negative gate bias stress in 4H-SiC MOSFETs by fast on-the-fly method

The threshold voltage shift in NO-annealed 4H-SiC MOSFETs during negative gate bias stress was investigated with a fast on-the-fly method for p-channel devices while considering the stress–time dependence of the slope of the drain current–gate voltage characteristics. With the proposed method, the threshold voltage shift was accurately measured over a wide time range from hundreds of nanoseconds. The negative threshold voltage shift exhibited power-law time dependence at room temperature and logarithmic time dependence at 423 K, suggesting that interface trap generation is observable at room temperature and thermally-assisted hole trapping in SiO2 dominates at high temperatures.

A Study on the Temperature-Dependent Operation of Fluorite-Structure-Based Ferroelectric HfO2 Memory FeFET: Pyroelectricity and Reliability

We report on the high-temperature operation and reliability of the Si-doped hafnium oxide (HSO) ferroelectric FET (FeFET) emerging memory. In this study, we explore the role of high-temperature operation of the ferroelectric (FE) material on the FeFET in the temperature range of 40-120 °C. The inverse memory window (MW) dependence on temperature leads to a very small MW size (~300 mV) at 120 °C. The recovery of MW size at room temperature (RT) indicates a potential pyroelectric effect as a cause for MW closure upon high-temperature operation. The FeFET state readout shows pronounced effects to erase (ER) threshold voltage (Vth) shift, due to the decrease in remnant polarization and improved substrate Vth shift as the temperature increases. The endurance reliability measured for temperature range (-40 °C to 40 °C) with 105 cycles shows a maximized initial MW at low temperatures, whereas higher postcycling interface trap generation occurs as the temperature increases. The FeFET 10 h retention tests at 0 °C and 40 °C were extrapolated to ten years and indicated stable properties independent of temperature. The depolarization field (Ed) dependence on the FeFET stack parameters is studied based on an analytical formula. The Ed decreases with increased permittivity of the FE, interface layer (IL), and increased FE film thickness. Substrate doping and temperature seem to have a small impact on E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , whereas the FE-IL area ratio tuning below unity lowers the E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> . The role of pyroelectric effect on the FeFET memory and operating temperature-induced endurance and retention reliability concerns are discussed.

Understanding Frequency Dependence of Trap Generation Under AC Negative Bias Temperature Instability Stress in Si p-FinFETs

In this letter, we present an experimental study on the frequency ( f ) dependence of trap generation under AC negative bias temperature instability (NBTI) stress in Si p-channel fin field-effect transistors (p-FinFETs), by adopting the direct-current current voltage (DCIV) method and an energy profiling technique. The interface trap generation ( $\Delta ~\text{N}_{IT}$ ) and bulk trap generation ( $\Delta ~\text{N}_{OT}$ ) are separated from the measured DCIV data and their ${f}$ dependences are independently investigated. The DCIV results indicate that the observed strong ${f}$ dependence of trap generation is primarily attributed to the ${f}$ -dependent $\Delta ~\text{N}_{OT}$ that exhibits a 36% reduction when ${f}$ increases from 10 Hz to 1 MHz. Furthermore, this ${f}$ -dependent $\Delta ~\text{N}_{OT}$ is mainly distributed between ${\text{E}_{v}}$ and ${\text{E}_{i}}$ , and exhibits a visible ${f}$ -dependent peak of energy density around ${\text{E}_{c}}$ .

Scalable compact modeling of trap generation near the EB spacer oxide interface in SiGe HBTs

This paper presents a physics-based scalable formulation for interface trap generation in the vicinity of the emitter-base spacer oxide interface in advanced SiGe HBTs. Aging tests were performed for various emitter dimensions to investigate the scalability of the dynamics of hot-carrier degradation. An improved formulation of the bond dissociation rate is also proposed incorporating a scaling rule depending on the avalanche current density. The hydrogen diffusion through the EB spacer has been modeled using an RC ladder network and has been scaled according to the hydrogen diffusion volume. Its accuracy has been validated over a wide range of aging tests and various geometry features.

Effect of Simultaneous Mechanical and Electrical Stress on the Electrical Performance of Flexible In-Ga-Zn-O Thin-Film Transistors.

We investigated the effect of simultaneous mechanical and electrical stress on the electrical characteristics of flexible indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). The IGZO TFTs exhibited a threshold voltage shift (∆VTH) under an application of positive-bias-stress (PBS), with a turnaround behavior from the positive ∆VTH to the negative ∆VTH with an increase in the PBS application time, whether a mechanical stress is applied or not. However, the magnitudes of PBS-induced ∆VTH in both the positive and negative directions exhibited significantly larger values when a flexible IGZO TFT was under mechanical-bending stress than when it was at the flat state. The observed phenomena were possibly attributed to the mechanical stress-induced interface trap generation and the enhanced hydrogen diffusion from atomic layer deposition-grown Al2O3 to IGZO under mechanical-bending stress during PBS. The subgap density of states was extracted before and after an application of PBS under both mechanical stress conditions. The obtained results in this study provided potent evidence supporting the mechanism suggested to explain the PBS-induced larger ∆VTHs in both directions under mechanical-bending stress.

Influence of Self-Heating Effect on Interface Trap Generation in Highly Flexible Single-Crystalline Si Nanomembrane Transistors.

We analyze the interface trap states generated by the self-heating effect in flexible single-crystalline Si nanomembrane (sc-Si NM) transistors. Despite the excellent device performance (Subthreshold swing: ~61 mV/dec, Ion/off: ~109, Nit: ~5 × 1010 cm-2, µeff: ~250 cm²/V·s) and mechanical flexibility (RB,min ═ 1 mm) of sc-Si NM transistors on a polymer substrate, they are vulnerable to thermal reliability issues due to the poor thermal conductivity (κ < 1 W/m·K) of the polymer substrate. Understanding the detailed mechanism driving heat-related device degradation is key to improving device reliability, life expectancy, and overall device performance. Thus, a charge pumping method was employed to systematically analyze the device degradation caused by the self-heating effect. This enabled the interface trap density to be investigated for the flexible sc-Si NM transistors on a polymer substrate after a bias stress. For comparison, a heat spreading layer (HSL) made using a 1-µm thick Ag film (κ~400 W/m·K) was integrated into the sc-Si NM device to mitigate the self-heating effect. The results showed that the interface trap density was proportional to the self-heating effect. This facilitated the fundamental understanding of the self-heating effect of flexible sc-Si NM transistors, opening a robust route to realizing high performance flexible devices using sc-Si NM.

A Comparative Analysis of NBTI Variability and TDDS in GF HKMG Planar p-MOSFETs and RMG HKMG p-FinFETs

The time kinetics of threshold voltage shift ( $\Delta {V}_{T}$ ) is measured for negative-bias temperature instability (NBTI) and time-dependent defect spectroscopy (TDDS) experiments by an ultra-fast (10- $\mu \text{s}$ delay) method in gate-first high- ${k}$ metal gate (HKMG) planar p-MOSFETs and replacement metal gate HKMG p-FinFETs. The mean NBTI stress-recovery time kinetics obtained from multiple small-area MOSFETs and few-fin FinFETs at different values of stress bias ( ${V}_{\text {GSTR}}$ ) and temperature ( ${T}$ ) is modeled by uncorrelated contributions from interface ( $\Delta {V}_{\text {IT}}$ ) and bulk ( $\Delta {V}_{\text {OT}}$ ) trap generation and trapping of holes ( $\Delta {V}_{\text {HT}}$ ) in pre-existing defects. The time constant associated with recovery steps and the impact of each step for multiple TDDS sweeps on a single device and after NBTI in multiple devices are compared. The NBTI-induced $\Delta {V}_{T}$ distribution shape is verified using TDDS charge impact. The shift in mean and variance of NBTI-induced $\Delta {V}_{T}$ and post-stress ${V}_{T}$ distributions is modeled.

A 3-D TCAD Framework for NBTI, Part-II: Impact of Mechanical Strain, Quantum Effects, and FinFET Dimension Scaling

The TCAD framework developed in part-I of this paper is used to study the impact of fin length (FL) and fin width (FW) scaling on interface trap generation ( $\Delta \mathrm{V}_{\mathrm {IT}}$ ) during negative bias temperature instability (NBTI) in FinFETs. Structure and mechanical stress are obtained by Sentaurus process. Sentaurus device having capture-emission depassivation (CED) and multistate configuration (MSC) models are used for the trap kinetics. The mechanical strain and quantum confinement (QC) impacts are considered. The framework is validated using measured data from p-FinFETs having different FL and FW. The calibrated framework is used to estimate the impact of scaling on NBTI for 14-nm technology node and below. Different scenarios such as iso-stress bias ( $\mathrm{V}_{\mathrm {GSTR}}$ ) versus iso-stress overdrive (OD), and devices having iso-workfunction (WF) or iso-off current ( $\mathrm{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) are used for comparison.

Program/Erase Cycling Degradation Mechanism of HfO2-Based FeFET Memory Devices

The mechanism of memory window (MW) degradation of Hf0.5Zr0.5O2-based ferroelectric field-effect transistors (FeFETs) with program/erase (P/E) cycling is investigated. First, the P/E cycling properties of the FeFETs are characterized at different cycling voltages. Then, the midgap voltage method is proposed to address the underlying drivers for the threshold voltage shift and MW degradation by separating the effects of oxide-trapped charges and interface-trapped charges. The mechanism for different threshold voltage evolutions between programed and erased states during P/E cycling is revealed. Moreover, the amount of MW degradation is nearly equal to the difference of midgap voltage shift values between programed and erased states, and the interface trap generation contributes to the midgap voltage shift.

A 3-D TCAD Framework for NBTI—Part I: Implementation Details and FinFET Channel Material Impact

The time kinetics of interface trap generation and passivation ( $\Delta {N} _{\textsf {IT}}$ ) and its contribution ( $\Delta {V} _{\textsf {IT}}$ ) during and after negative bias temperature instability (NBTI) stress is calculated by using Sentaurus TCAD. The framework consists of Sentaurus process for the formation of realistic device structures and to obtain material and strain information, while Sentaurus device is used to implement the double-interface reaction–diffusion (RD) model for trap kinetics. Capture–emission depassivation (CED) model is used for the inversion layer hole and oxide electric field ( ${E} _{\textsf {OX}}$ )-assisted breaking of hydrogen (H) passivated defects at channel/gate insulator interface. Multistate configuration (MSC) model is used for diffusion of atomic and molecular hydrogen (H and H2) and further reactions with other H passivated defects in gate insulator bulk. Quantum effects are considered for hole density, and band structure calculation is used including mechanical strain for CED model parameters. Electron capture in the generated traps during recovery is calculated using transient trap occupancy model (TTOM) and implemented as a postprocessor. Measured data from silicon (Si) and silicon germanium (SiGe) p-channel FinFETs are used for validating the TCAD framework.

Impact Ionization and Interface Trap Generation in 28-nm MOSFETs at Cryogenic Temperatures

The characterization of impact-ionization (II) and stress-induced damage in 28-nm bulk n-channel MOSFETs is used to identify the mechanisms for carrier-induced interface trap generation (ITG) from 300 K to 77 K. The energy-driven paradigm of hot carrier effects is used to study carrier-induced ITG and its temperature dependence, and to analyze the influence of electron-electron scattering (EES) on carrier-induced degradation of ultra-short channel devices. The analysis clearly illustrates the significant role of EES in the hot (i.e., high-energy) carriers single particle mechanism of ITG, as well as its contribution to the cold (i.e., low-energy) carriers multiple particle mechanism of ITG. This is evidenced through extractions of ITG lifetime as a function of temperature and stress current from measurements of 28 nm n-channel devices. We apply a simple model to discuss the impact of EES on the experimentally observed trends for II and ITG rates.

Modeling of NBTI Kinetics in Replacement Metal Gate Si and SiGe FinFETs—Part-II: AC Stress and Recovery

An ultrafast (10- $\mu \text{s}$ delay) measurement technique is used to characterize ac negative-bias temperature instability-induced threshold voltage shift ( $\Delta \text {V}_\text {T}$ ) in replacement metal-gate-based high-K metal gate Si and SiGe p-FinFETs. Time kinetics of stress and recovery, voltage acceleration factor, temperature activation energy ( $\text {E}_\text {A}$ ), frequency (f), and pulse duty cycle (PDC) dependence are shown for different germanium percentages (Ge%) in the channel and nitrogen percentages (N%) in the gate insulator. A comprehensive physical model framework based on uncorrelated contributions from interface ( $\Delta \text {V}_\text {IT}$ ) and bulk oxide ( $\Delta \text {V}_\text {OT}$ ) trap generation and hole trapping in preexisting defects ( $\Delta \text {V}_\text {HT}$ ) is used to explain the measured data at different stress biases ( $\text {V}_\text {GSTR}$ ), temperatures (T), f, and PDCs. Direct-current I–V measurements are used to independently verify the interface-trap generation component for ac stress. End-of-life degradation for different processes under dc and ac conditions is estimated by using the calibrated model and compared to predictions from conventional analytical methods.