Abstract

The TCAD framework developed in part-I of this paper is used to study the impact of fin length (FL) and fin width (FW) scaling on interface trap generation ( $\Delta \mathrm{V}_{\mathrm {IT}}$ ) during negative bias temperature instability (NBTI) in FinFETs. Structure and mechanical stress are obtained by Sentaurus process. Sentaurus device having capture-emission depassivation (CED) and multistate configuration (MSC) models are used for the trap kinetics. The mechanical strain and quantum confinement (QC) impacts are considered. The framework is validated using measured data from p-FinFETs having different FL and FW. The calibrated framework is used to estimate the impact of scaling on NBTI for 14-nm technology node and below. Different scenarios such as iso-stress bias ( $\mathrm{V}_{\mathrm {GSTR}}$ ) versus iso-stress overdrive (OD), and devices having iso-workfunction (WF) or iso-off current ( $\mathrm{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) are used for comparison.

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