Interface Trap Distribution Research Articles

Analysis of interface trap induced ledge in β-Ga2O3 based MOS structures using UV-assisted capacitance–voltage measurements

A ledge feature in the capacitance–voltage (CV) profiles of Ga2O3 MOS (metal–oxide–semiconductor) capacitors is investigated using UV-assisted CV measurements. A model is presented whereby the capacitance ledge is associated with carrier trapping in deep-level states at the Al2O3/Ga2O3 interface. Following UV assisted emptying of interface traps at a constant bias, a voltage ramp toward flatband results in a CV ledge when the trap recombination current becomes equal to the quasi-static sweep charging current. The ledge continues until all the traps below the corresponding pinned surface potential have been filled. Varying the UV energy varies the ledge voltage range and allows a density of states to be determined as a function of energy. A broad interface state peak with maximum density ∼8 × 1012 cm−2 eV−1 for deep trap energies lying between 2.4 and 4.1 eV below the conduction band (CB) edge is extracted. Using the conductance method, the interface trap density is also found to rise toward the CB edge in the range 0.25–0.45 eV below the CB edge, reaching a maximum density of ∼1 × 1012 cm−2 eV−1. Combining these two techniques, an interface trap distribution is estimated for almost the entirety of the bandgap of Ga2O3. This novel technique probes deep interface states where standard methods fail to quantify interface states reliably.

An approach for extracting the SiC/SiO2 SiC MOSFET interface trap distribution and study during short circuit

The high trap density at the SiC/SiO2 interface is still the major reliability issue of silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs). In this paper, we analyse the influence of the channel region and JFET region on the C-V curve from the band perspective. We proposed an approach to extract the oxide interface characteristics of a SiC MOSFET by fitting the measured C-V characteristic curve with the TCAD simulated curve. Then, the extracted SiC/SiO2 interface characteristics were verified by fitting the measured and simulated I-V curves and threshold voltages (VTH) at different lattice temperatures. Next, the extracted interface characteristics and the fixed interface charge were separately added to the TCAD model for comparison of the short-circuit simulations. It was found that the former model failed earlier than the latter and that the peak short-circuit current value was lower. The causes of these two phenomena are attributed to the different leakage degrees of the hole current in the Pbase region below the channel caused by interface traps and the difference in the channel mobility, respectively. Last, according to current shunt theory, P-type blocks were added below the JFET area to reduce the current during a short-circuit transient, thus improving the capacity to withstand a short circuit by approximately 22.4%.

Visualization of Interface Trap Distribution for Pd/AlN/6H-SiC and Pd/HfO<sub>2</sub>/6H-SiC MOS Capacitors at 700 K

Comparison of C-V characteristics and interface trap distribution for 6H-SiC MOS capacitor with AlN and HfO2 as high-k dielectric are presented. It is observed that the transition from accumulation to inversion requires a small change in gate voltage for HfO2 compared to AlN. Furthermore, larger shift in flat band voltage with respect to frequency is observed in case of AlN. A larger change in capacitance with respect to voltage and flat band voltage shift with respect to frequency for AlN indicated a poor choice for MOS capacitor compared to HfO2.

Impact of interface trap charge and temperature on the performance of epitaxial layer tunnel field effect transistor

A simulation study of the impact of interface traps on the performance of the Epitaxial Layer Tunnel Field Effect Transistor (ETLTFET) having Si(1-x)Gex as source material is investigated in terms of interface Trap distribution, energies, random trap fluctuation (RTF), and temperature in comparison with FinFET. The study revealed a similar trend of Vth shift for ETLTFET and FinFET for a given trap type. For both ETLTFET and FinFET, the donor interface trap with energy above the semiconductor mid band gap can cause a shift in ION as well as IOFF, while the acceptor interface trap has a comparatively wider energy range. Again, trap induced SS degradation is minor in ETLTFET than its counterparts. In the case of RTF in nano-scaled devices, the fluctuations in ION and Vth induced by interface traps are found to vary with the position of the trap, and the variations at ETLTFET are relatively more minor than the FinFET. Furthermore, the presence of interface trap charges alters the device's temperature sensitivity which could be detrimental for the device to be utilized in sensor applications.

An Iterative Surface Potential Algorithm Including Interface Traps for Compact Modeling of SiC-MOSFETs

Surface potential-based compact models are an essential link between circuit simulation and technology due to their physical base. Such models are particularly important for the development of devices and circuits based on new wide-bandgap semiconductors such as silicon carbide (SiC) where additional physical phenomena in comparison to silicon are considered. An efficient computation of the surface potential ( $\Phi _{\text {S}}$ ) is one of the core components of $\Phi _{\text {S}}$ -based compact models. We developed a fast and robust iterative algorithm for the surface potential, which takes the specific interface trap distribution of SiC-MOSFETs into account. Therefore, a new initial guess is derived, which reduces the number of required iteration steps by 40% in contrast to the common initial guess for silicon devices. Furthermore, different starting equations and types of iteration steps are compared in terms of convergence speed and stability over a wide range of densities of interface traps, technology parameters, and operating conditions.

Investigation of interface traps at Si/SiO2 interface of SOI pMOSFETs induced by Fowler–Nordheim tunneling stress using the DCIV method

The changes of interface trap density and distribution at the Si/SiO2 interface in partially depleted SOI MOSFETs were investigated by direct-current current–voltage (DCIV) method before and after Fowler–Nordheim tunnelling stress condition. The equivalent density and energy level of interface trap were obtained by combining the DCIV measurement results with the theoretical calculation using the least square method. It is concluded that the interface trap density increased as applying F–N stress due to the generation of Si dangling bond and the trapped charge at the Si/SiO2 interface, and the equivalent energy level of interface trap become close to the midgap with stress time increasing. In addition, interface trap density NIT as a function of their energy level EIT can be achieved, which were typical “U-shape” curves, and the interface trap density near midgap increases obviously as the F–N stress time increasing. An effective method is proposed to evaluate the interface state of SOI devices suffered electrical stress or other damages.

A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements.

Charge pumping test technique using CMOS ring oscillator on leakage issue

With the scaling down of CMOS devices, traditional charge pumping measurement used to extract interface trap distribution is confronted with great challenge due to large leakage current. Special pulses with high frequency and short transition time are required to accurately extract the interface trap density, which places great demands on equipments in current charge pumping measurements. In this paper, a new charge pumping test technique is proposed, in which suitable voltage pulses are produced by CMOS ring oscillator instead of equipments. Simulation results show that frequency of the voltage pulses generated by ring oscillator can be readily greater than 1GHz, and rising/falling time is around 60ps. Due to these superiorities, new technique can measure interface trap density more exactly by totally eliminating the influence of gate leakage without any handling with the leakage current.

Recent Progress in SiC and GaN Power Devices

Owing to low conduction/switching loss, high switching frequency and high operating temperature, wide bandgap SiC and GaN power devices are attractive for next-generation power electronic systems with increased efficiency and power density. Because of the superior performance, SiC and GaN power devices could be in position to compete with the mainstream Si power devices in a variety of applications, including household appliances, photovoltaic inverters, electric vehicles, data centers, etc. Despite numerous research efforts devoted to material growth, device fabrication and circuit demonstration in the past decades, wide bandgap power semiconductor devices are still confronted with challenges that need to be addressed through new structure design and advanced process development. In this talk, we will review recent progress in SiC and GaN power devices, including the following. (1) High-density of interface traps usually exist at the gate-oxide/SiC interface in SiC MOSFETs, presenting a critical challenge to the channel mobility and device stability. Interface engineering techniques for SiC MOSFETs (e.g. NO/N2O annealing, P incorporation, metal interfacial-layer, high-k dielectric deposition, etc.) and their impact on interface trap distribution as well as channel mobility will be discussed. (2) Long-term reliability of SiC MOSFETs with special focus on time-dependent dielectric breakdown (TDDB) will be presented. (3) We will introduce our latest progress in design and fabrication of super junction SiC devices, which can break the fundamental limit of the conventional unipolar devices. (4) In GaN-based lateral power devices, the 2DEG channel is an inherent normally-on channel, due to the spontaneous and piezoelectric polarization effects. To achieve fail-safe operation and simpler gate drive circuit, normally-off device technology including p-(Al)GaN cap, barrier recess and plasma treatment in the gate region will be introduced and compared. (5) Gate stack engineering techniques toward high-reliability GaN MIS-HEMTs/FETs will also be presented.

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.

Interface traps contribution to capacitance of Al2O3/(GaN)AlGaN/GaN heterostructures at low frequencies

Influence of interface traps at Al2O3/(GaN)/AlGaN interface on low and high frequency capacitance of Al2O3/(GaN)/AlGaN/GaN heterostructure capacitor was studied. New features were observed in the capacitance curves. Obtained experimental results were modeled and simulated and accordance with the experiment has been obtained. For lower frequencies a new capacitance peak in the depletion and increase of the capacitance in a plateau region were measured. The capacitance peak in the depletion region was successfully explained by a capacitance response of the interface traps with U-shape density distribution. On the other hand the increase of the capacitance plateau was modeled by the homogeneous interface trap distribution. We assume that the traps located near the band edges having the highest density are able to respond to the low frequency measuring.

Metal oxide-graphene field-effect transistor: interface trap density extraction model.

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current–gate voltage relationship Ids–Vgs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance–gate voltage Ctot–Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

Deposition of Intrinsic a-Si:H by ECR-CVD to Passivate the Crystalline Silicon Heterointerface in HIT Solar Cells

We have deposited intrinsic amorphous silicon (a-Si:H) using the electron cyclotron resonance (ECR) chemical vapor deposition technique in order to analyze the a-Si:H/c-Si heterointerface and assess the possible application in heterojunction with intrinsic thin layer (HIT) solar cells. Physical characterization of the deposited films shows that the hydrogen content is in the 15–30% range, depending on deposition temperature. The optical bandgap value is always comprised within the range 1.9–2.2 eV. Minority carrier lifetime measurements performed on the heterostructures reach high values up to 1.3 ms, indicating a well-passivated a-Si:H/c-Si heterointerface for deposition temperatures as low as 100 oC. In addition, we prove that the metal–oxide–semiconductor conductance method to obtain interface trap distribution can be applied to the a-Si:H/c-Si heterointerface, since the intrinsic a-Si:H layer behaves as an insulator at low or negative bias. Values for the minimum of D it as low as 8 × 1010 cm-2⋅eV-1 were obtained for our samples, pointing to good surface passivation properties of ECR-deposited a-Si:H for HIT solar cell applications.

Fully subthreshold current-based characterization of interface traps and surface potential in III–V-on-insulator MOSFETs

We report characterization of the interface trap distribution (Dit(E)) over the bandgap in III–V metal–oxide–semiconductor field-effect transistors (MOSFETs) on insulator. Based only on the experimental subthreshold current data and differential coupling factor, we simultaneously obtained Dit(E) and a nonlinear mapping of the gate bias (VGS) to the trap level (Et) via the effective surface potential (ψS,eff). The proposed technique allows direct extraction of the interface traps at the In0.53Ga0.47As-on insulator (-OI) MOSFETs only from the experimental subthreshold current data. Applying the technique to the In0.53Ga0.47As channel III–V-OI MOSFETs with the gate width/length W/L=100/50, 100/25, and 100/10μm/μm, we obtained Dit(E)≅1011–1012eV−1cm−2 over the bandgap without the dimension dependence.

MONOS 플래시 메모리의 Nitride 트랩 분석

This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.

Two-dimensional (2D) transition metal dichalcogenide semiconductor field-effect transistors: the interface trap density extraction and compact model

A surface potential-based low-field drain current compact model is presented for two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductor field-effect transistors that takes into account the effect of interface trap states on device current–voltage (Ids–Vgs) characteristics and transconductance gm. The presence of interface trap states detrimentally affects device Ids–Vgs performance. Minimal work exists on the extraction of trap states (cm−2 eV−1) of MoS2/high-K dielectric/metal-gate stacks. Additionally, there is a lack of compact models for 2D TMD MOSFETs that can take into account the effect of trap states on device Ids–Vgs performance. This study presents a method to extract the interface trap distribution of MoS2 MOSFETs using a compact model. Presented as part of the model is a surface potential/interface trap charge self-consistent calculation procedure and a drain current expression that does not need numerical integration. The model is tested against reported experimental Ids–Vgs data, and excellent agreement is found between the experiment and the model.

Mechanisms of thermally induced threshold voltage instability in GaN-based heterojunction transistors

In this work, we attempt to reveal the underlying mechanisms of divergent VTH-thermal-stabilities in III-nitride metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) and MOS-Channel-HEMT (MOSC-HEMT). In marked contrast to MOSC-HEMT featuring temperature-independent VTH, MIS-HEMT with the same high-quality gate-dielectric/III-nitride interface and similar interface trap distribution exhibits manifest thermally induced VTH shift. The temperature-dependent VTH of MIS-HEMT is attributed to the polarized III-nitride barrier layer, which spatially separates the critical gate-dielectric/III-nitride interface from the channel and allows “deeper” interface trap levels emerging above the Fermi level at pinch-off. This model is further experimentally validated by distinct VG-driven Fermi level movements at the critical interfaces in MIS-HEMT and MOSC-HEMT. The mechanisms of polarized III-nitride barrier layer in influencing VTH-thermal-stability provide guidelines for the optimization of insulated-gate III-nitride power switching devices.

Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack ( Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.

Interface trap characterization of atomic layer deposition Al2O3/GaN metal-insulator-semiconductor capacitors using optically and thermally based deep level spectroscopies

Quantitative measurements of interface state density and energy distribution profiles within Al2O3/GaN interfaces were obtained by constant capacitance deep level transient spectroscopy and deep level optical spectroscopy (CC-DLTS/DLOS). The new application of CC-DLOS to interface state measurement is described, which allows interrogation of very deep interface states. A series of Al2O3/GaN metal-insulator-semiconductor (MIS) devices prepared as a function of Al2O3 thickness via atomic layer deposition, on NH3-MBE-grown n-type Ga-polar GaN layers enabled a systematic study. The overall shape and magnitude of the interface trap distribution, Dit, were determined to be nearly identical, independent of Al2O3 thickness. The Al2O3/GaN Dit spectra had an overall U-shape with Dit ∼1012 cm−2 eV−1 near the conduction band edge, ∼1011 cm−2 eV−1 mid-gap, and ∼1014 cm−2 eV−1 near the valence band edge. However, the interface states near the GaN conduction band showed a slight inverse dependence on Al2O3 thickness, suggestive of annealing effect during deposition. The high near valence band state concentrations are consistent with expectations from residual carbon impurities at the GaN surface. A method for discriminating between bulk and interface states in the CC-DLTS signal is demonstrated, using the results on MIS capacitors in combination with spectroscopy results on a Schottky diode structure.

The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET

The impact of interface/border defect on performance and reliability was investigated for gate-first and gate-last high-k/metal-gate CMOSFET. For high-k/metal-gate CMOSFET, VFB roll-off is critical as effective oxide thickness (EOT) scales below 15 angstrom (Å) especially for metal gate-first device with an extra capping layer to adjust VTH. By proposing a model of metal-gate process induced interface trap releasing oxygen, the vertical and lateral interface trap distribution and the dependence of interfacial layer (IL) on VFB roll-off phenomena can be well interpreted. In this work, we found that VFB roll-off can be improved by reducing oxygen vacancy (VO) at the HfO2/IL interface with suppression of oxygen diffusion from high-k to IL. By the way, a metal gate-last process with lower interface trap was proposed to minimize VO formation by suppress oxygen releasing, thus optimize a 28nm 15Å EOT HfO2/metal-gate CMOSFET with low VFB–EOT roll-off, it can be a reference for sub 22nm CMOSFET with thin EOT (<15Å) design.