Network Interface Research Articles

Indian Sign Language Recognition Using 2-D Convolution Neural Network and Graphical User Interface

Indian Sign Language Recognition Using 2-D Convolution Neural Network and Graphical User Interface

MERIDIAN open-source software for deep learning-based acoustic data analysis

Deep neural networks have the potential to transform our approach to developing acoustic detection and classification models, enabling acousticians to develop or re-purpose such models through a fully data-driven approach requiring minimal knowledge of signal processing, algorithm design, and programming. However, open-source software to facilitate this data-driven workflow is currently lacking. MERIDIAN is working towards filling this gap through the development of several open-source software products, including the Python package Ketos and the MAIPL (Marine AI PLatform) suite of web applications. While Ketos provides a high-level programming interface for training deep neural networks at detecting and classifying sounds, MAIPL is a modular cloud computing service that supports the full model-development workflow. In this contribution, an overview of Ketos and MAIPL will be given and their functionalities will be demonstrated through their application to the HALLO (Humans and ALgorithms Listening for Orcas) project. We highlight one of the MAIPL tools, the MAIPL-Annotator, which provides a user-friendly interface for collaboratively annotating sound samples and validating model predictions. Future developments will also be described, highlighting new MAIPL applications under development such as the MAIPL-Adapter, a tool for adapting acoustic deep learning models to new acoustic environments.

Energy management optimization of integrated energy system with electric hydrogen hybrid energy storage

Abstract Integrated energy system (IES) has attracted wide attention as an efficient solution to a comprehensive utilization of hybrid energy system including electricity, heat, and hydrogen in recent years. This paper investigates the stochastic optimal operation for the micro integrated electric power, heat, and hydrogen delivery system. Firstly, the mathematical model of the micro integrated energy system for residential communities and other similar scenarios is discussed, including the energy interface, power microgrid, micro-heat system and micro-hydrogen system with considerations of distributed energy supply, energy storage, load, upstream energy network interface and their mathematical models. Secondly, the correlated uncertainty, such as wind power, solar power, and loads, are considered and handled in micro integrated energy system. Finally, a scenario-based approach is proposed for the stochastic operation of micro integrated energy system. The objective function is formulated to minimize the expected total operation and environmental costs, the hourly schedule of controllable components in micro integrated energy system. Numerical results demonstrated that the effectiveness of the proposed method. The correlated uncertainty and the corresponding impacts are accurately presented in the optimization model.

Embedded Hardware/Software CAN Node Design for Engineering and Research in the Automotive Application Field

This work proposes a design of an embedded CAN node in the form of an electronic development board. The entire circuit is developed around an 8-bit PIC18Fxxxx microcontroller family in order to increase the optimal cost to performance ratio. The proposed board integrates the three CAN standards: physical, link and application layers. In addition to the CAN communication chain, the solution integrates the necessary modules to accomplish a complete application without the need of external hardware. It includes an input button and output LEDs, an integrated LCD display connector, a real time clock with active time memory buck up, a micro SD card for data storage, ESP8260 network interface for internet of things applications (IoT), several supported protocols interfaces like USB & RS232 and on board DS18B20 thermal sensor based on ONE Wire protocol. In addition to these hardware features, a complete Hardware Abstraction Layer (HAL) has been developed to manage the board software part. In the end, the whole solution validation (Hardware/software) will be done in real case studies and test scenarios that combine two or more modules at the same time. The results of every experiment are verified based on real time signal analysis using a digital oscilloscope.

Aggregation arrangement features of network interface channels in multiprocessor computing systems

The paper identifies ways to increase the multiprocessor computing system performance by reorganizing the architecture of its network interface. It is shown that the computational parallelization performance significantly depends on many factors, the most essential of which is the data transfer between the boundary nodes of a multiprocessor system, which is the algorithm's slowest part and can significantly reduce the effect of increasing the number of processors. Hence, it was established that improving the multiprocessor systems performance by reorganizing the network interface structure is relevant interesting nowadays, and its study is at the active development stage. The research aims at the aggregation arrangement of network interface channels in multiprocessor computing systems. It is shown that the main channel aggregation mode advantage is that the data interchange speed is significantly increased, as well as the reliability of the cluster system.

Micro-Grid Simulation and Integration with GRID using 13 Level Inverter

The need for renewable energy systems (RES) continues to grow, and research into wind and solar systems has accelerated in recent years. At the moment, the world's energy requirements are heavily reliant on fossil fuels, which are on the verge of extinction. Renewable energy demand will skyrocket in the next years. Our study demonstrates a robust energy generating system that utilises photovoltaic MPPT and a 13-level inverter system in MATLAB simulink to maximise the output of the solar panel. To optimise the advantages of such network interface distribution systems, a control approach is developed. The inverter is programmed to perform several purposes, including active power filtering. Thus, the inverter may be employed as a power converter to power the network's renewable energy sources. The MATLAB / Simulink simulation is used to execute and verify all of the analyses by subjecting the system to dynamic load conditions.

Forecasting Network Interface Flow Using a Broad Learning System Based on the Sparrow Search Algorithm.

In this paper, we propose a broad learning system based on the sparrow search algorithm. Firstly, in order to avoid the complicated manual parameter tuning process and obtain the best combination of hyperparameters, the sparrow search algorithm is used to optimize the shrinkage coefficient () and regularization coefficient () in the broad learning system to improve the prediction accuracy of the model. Second, using the broad learning system to build a network interface flow forecasting model. The flow values in the time period are used as the characteristic values of the traffic at the moment . The hyperparameters outputted in the previous step are fed into the network to train the broad learning system network traffic prediction model. Finally, to verify the model performance, this paper trains the prediction model on two public network flow datasets and real traffic data of an enterprise cloud platform switch interface and compares the proposed model with the broad learning system, long short-term memory, and other methods. The experiments show that the prediction accuracy of this method is higher than other methods, and the moving average reaches 97%, 98%, and 99% on each dataset, respectively.

Towards a Design Theory for Resilient (Sociotechnical, Cyber-Physical, Software-intensive and Systems of) Systems

Resilience, as a property of a system, must transition from just a buzzword to an operational paradigm for system management, especially under future climate change. Identifying the need for system resilience requires defining the system. Revolutionary advances in hardware, networking, information and human interface technologies require new ways of thinking about how sociotechnical, cyber-physical, and systems of systems are conceptualized, built and evaluated. The aim of this paper is to start a development process for a design theory (DT) for resilient systems (DT4RS). With the help of DT4RS, communities are able to develop and operate different information and security technologies, and share knowledge and best practices.

Intelligent Monitoring System for Prison Perimeter Based on Cloud Intelligence Technology

In order to realize the security of prison perimeter, a prison perimeter intelligent monitoring system based on cloud intelligence technology is designed. Based on the multisupply chain collaboration framework, the prison network interface submodule and sniffer monitoring structure are connected on demand to complete the hardware execution environment of the prison perimeter intelligent monitoring system. Analyze the specific service mode of the cloud smart technology host, set the necessary cloud smart technology service monitoring protocol, judge the processing information parameters, select the prison perimeter remote communication port number, set the prison perimeter network IP address and password program, complete the construction of the software execution environment of the monitoring system, and intelligently monitor and track the abnormal conditions around the prison; combined with the relevant hardware and software structure, the design of prison perimeter intelligent monitoring system based on cloud intelligence technology is realized. The experimental results show that the DPI index of the designed system has an obvious upward trend, and the processing results are close to the original image results to avoid the impact caused by the change of monitoring scene.

A novel 1D/2D interpenetrating network architecture of MXene/cellulose composite microfiber and graphene for broadband microwave absorption

Exploiting diverse electromagnetic wave absorbers by introducing novel nanomaterials is an attractive strategy to address the issue of electromagnetic pollution. Ti3C2Tx MXene has been considered as a promising candidate for efficient microwave absorption but remains a contradiction between maintaining impedance matching and enhancing dielectric loss. To overcome this challenge, a unique 1D/2D interpenetrating network architecture consisting of 1D MXene/cellulose (MC) composite microfibers and a graphene porous framework is designed in this work. Ti3C2Tx MXene is loaded on flexible carboxymethyl cellulose microfibers to form a 1D core–shell structure by self-assembly and cross-linked with reduced graphene oxide layers via hydrothermal reduction to prepare the MC/graphene aerogel (MCGA). The intricate cross-linking network and abundant binding interface in the aerogel promote the conductive loss and polarization loss, while the MC microfiber improves the overall impedance matching degree by ameliorating the internal aperture structure. The optimal reflection loss of MCGA is −87.48 dB and the broadest effective absorption bandwidth (EAB) reaches 10.4 GHz, which is superior to almost all conventional MXene-based microwave absorbers. Moreover, MCGA exhibits multifunctional attributes including hydrophobicity, thermal insulation, and compressibility, revealing the validity and advantage of this design route.

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Network-on-chip (NoC) provides solution to overcome the complications of the on-chip interconnect architecture in multi-core systems. It mainly consists of router, links and network interface. An essential component of on-chip router is an arbiter that significantly impacts the performance of the router. The arbiter should provide fast and fair arbitration when it is placed in Critical Path Delay (CPD) systems. The main aim of this research work is to design a novel arbiter for an effective network scheduler in complex real time applications. At the same time resource allocation and power consumption should be very low. Previously, a novel gate level Ping Lock Arbiter (PLA) is designed to overcome the limited fair arbitration in Improved Ping Pong Arbiter (IPPA) with less delay. But the chip size and power consumption are very high. To overcome this problem, an Effective Gate Diffusion Input (EGDI) logic-based CMOS scheme is used to design a novel Compact Ping Lock Arbiter (CPLA). The proposed CPLA is compared with the existing PLA based on static CMOS scheme. The comparison between the conventional and proposed arbiter is carried out to analyze the area, delay and power by using Tanner Tool 14.1 with 250nm and 45nm technology. The proposed CPLA is suitable for compact and smart applications with glitch free and fair arbitration. The proposed CPLA presents 41.2% reduction in total area consumption. It also provides 47.12% average Area and Power Product (APP) reduction when compared to the existing 4-bit PLA. Similarly, the proposed 8-bit CPLA shows 49.48% average APP product shrinkage when compared to conventional 8-bit PLA. For low power and area constraint applications, the proposed CPLA with EGDI is best in comparison to the static CMOS based ping lock round robin arbiter. Therefore, the results demonstrate that the proposed CPLA achieves low power and consumes less area than the existing ping lock arbiter.

Securing InfiniBand Networks with the Bluefield-2 Data Processing Unit

Interest in securing InfiniBand networks with encryption is growing. However, the performance benefit realized by InfiniBand’s use of Direct Memory Access (DMA) to bypass the kernel and avoid intervention from host Central Processing Units (CPUs) is at odds with IP datagram encryption techniques. Encryption forces data through the CPU before transmission and decryption, incurring multiple clock cycles. The Bluefield-2 Data Processing Unit (DPU) is Nvidia-Mellanox’s latest system on chip that combines a high-performance, programmable processor, network interface card (NIC), and flexible hardware accelerators. This research characterizes the Bluefield-2’s capability to accelerate IPsec encryption in hardware. Results show that the Bluefield-2’s hardware accelerators are capable of supporting a secure IPsec tunnel with a throughput of nearly 16 Gb/s. Offloading IPsec encryption operations to the hardware accelerators on the Bluefield-2 is a promising method for adding confidentiality, integrity, and authentication to InfiniBand networks.

Stability of Multimicrogrids: New Certificates, Distributed Control, and Braess’s Paradox

This paper investigates the theory of resilience and stability in multi-microgrid networks. We derive new sufficient conditions to guarantee small-signal stability of multi-microgrids in both lossless and lossy networks. The new stability certificate for lossy networks only requires local information, thus leads to a fully distributed control scheme. Moreover, we study the impact of network topology, interface parameters (virtual inertia and damping), and local measurements (voltage magnitude and reactive power) on the stability of the system. The proposed stability certificate suggests the existence of Braess's Paradox in the stability of multi-microgrids, i.e. adding more connections between microgrids could worsen the multi-microgrid system stability as a whole. We also extend the presented analysis to structure-preserving network models, and provide a stability certificate as a function of original network parameters, instead of the Kron reduced network parameters. We provide a detailed numerical study of the proposed certificate, the distributed control scheme, and a coordinated control approach with line switching. The simulation shows the effectiveness of the proposed stability conditions and control schemes in a four-microgrid network, IEEE 33-bus system, and several large-scale synthetic grids.

Wireless Readout of Resistive Sensors

In this paper we present a method for wireless readout of resistive sensors. Our approach is based on the topology where resistive sensor and reference resistor form a voltage divider network, with reference resistor connected in parallel with a varactor diode. Variation of the sensor resistance causes voltage changes over the varactor, and consequently capacitance of the varactor. Varactor is placed in the LC circuit, thus a change of resonant frequency occurs due to the change of the sensor resistance. Resonant frequency can be detected with external readout inductor connected to the inductance measurement device. The proposed method is theoretically analyzed and experimentally verified with discrete resistors and resistive force sensor. Main advantages of our approach are: (1) it keeps simplicity of the voltage divider network interface with resistive sensors, (2) energy autonomy of sensor tag is extended as energy needed for readout is provided by an external reader, (3) proposed method can be easily adopted for various dynamic range of resistive sensors, and (4) two methods for power supply (battery and energy harvesting with inductive coupling) were analyzed.

End-to-end Characterization of Game Streaming Applications on Mobile Platforms

With the advent of 5G, supporting high-quality game streaming applications on edge devices has become a reality. This is evidenced by a recent surge in cloud gaming applications on mobile devices. In contrast to video streaming applications, interactive games require much more compute power for supporting improved rendering (such as 4K streaming) with the stipulated frames-per second (FPS) constraints. This in turn consumes more battery power in a power-constrained mobile device. Thus, the state-of-the-art gaming applications suffer from lower video quality (QoS) and/or energy efficiency. While there has been a plethora of recent works on optimizing game streaming applications, to our knowledge, there is no study that systematically investigates the <QoS, Energy> design pairs on the end-to-end game streaming pipeline across the cloud, network, and edge devices to understand the individual contributions of the different stages of the pipeline for improving the overall QoS and energy efficiency. In this context, this paper presents a comprehensive performance and power analysis of the entire game streaming pipeline consisting of the server/cloud side, network, and edge. Through extensive measurements with a high-end workstation mimicking the cloud end, an open-source platform (Moonlight-GameStreaming) emulating the edge device/mobile platform, and two network settings (WiFi and 5G) we conduct a detailed measurement-based study with seven representative games with different characteristics. We characterize the performance in terms of frame latency, QoS, bitrate, and energy consumption for different stages of the gaming pipeline. Our study shows that the rendering stage and the encoding stage at the cloud end are the bottlenecks to support 4K streaming. While 5G is certainly more suitable for supporting enhanced video quality with 4K streaming, it is more expensive in terms of power consumption compared to WiFi. Further, fluctuations in 5G network quality can lead to huge frame drops thus affecting QoS, which needs to be addressed by a coordinated design between the edge device and the server. Finally, the network interface and the decoder units in a mobile platform need more energy-efficient design to support high quality games at a lower cost. These observations should help in designing more cost-effective future cloud gaming platforms.

Understanding I/O Direct Cache Access Performance for End Host Networking

Direct Cache Access (DCA) enables a network interface card (NIC) to load and store data directly on the processor cache, as conventional Direct Memory Access (DMA) is no longer suitable as the bridge between NIC and CPU in the era of 100 Gigabit Ethernet. As numerous I/O devices and cores compete for scarce cache resources, making the most of DCA for networking applications with varied objectives and constraints is a challenge, especially given the increasing complexity of modern cache hardware and I/O stacks. In this paper, we reverse engineer details of one commercial implementation of DCA, Intel's Data Direct I/O (DDIO), to explicate the importance of hardware-level investigation into DCA. Based on the learned knowledge of DCA and network I/O stacks, we (1) develop an analytical framework to predict the effectiveness of DCA (i.e., its hit rate) under certain hardware specifications, system configurations, and application properties; (2) measure penalties of the ineffective use of DCA (i.e., its miss penalty) to characterize its benefits; and (3) show that our reverse engineering, measurement, and model contribute to a deeper understanding of DCA, which in turn helps diagnose, optimize, and design end-host networking.

Implementation of Dynamic and Efficient Virtual Channel Router for Network on Chip with Virtual Channel Arbitration Reduction and Parallel Switch Allocation Unit

— Network on chip (NoC) is a new method of interconnecting modules in system on chip (SoC). Now a day, it is believed that this new communication subsystem will replace the bus-based architecture and will become dominant in SoC design technology. The performance of NoC mainly depends on the router so it is considered as the crucial part in the NoC design. This paper describes the different factors which affect the NoC performance and provides solution to solve these problems. The proposed router has three architectural modifications which makes it dynamic and efficient as compare to generic virtual channel router. This paper introduced the dynamic buffer allocation scheme in which virtual channels and buffer slots are selected and allocated dynamically depending on the network traffic conditions in real time which in turn increases the throughput. In this paper, we have focused on optimizing the virtual channel arbitration (VA) unit design and switch allocation (SA) unit design as well as focusing the maximum utilization of buffer so that it will result in minimizing the latency, area and power. The source code of the router is written in VHDL hardware description language and the simulation and synthesizing the router is done in Xilinx ISE Design Suite 13.1. The parameters like area, frequency, delay, power, latency and throughput are calculated. The results of this modified virtual channel router are compared with the generic virtual channel router. Keywords—Intellectual Property (IP), Network on Chip (NoC), Network Interface (NI), Switch allocation (SA), System-on-Chip (SoC), Virtual channel (VC), Virtual channel arbitration (VA)

Proffering Secure Energy Aware Network-On-Chip (Noc) Using Incremental Cryptogine

Network-on-chip (NoC) is an integrated circuit network-based communications subsystem that usually operates between System on chip (SoC) systems. Security risks, including hidden data gathering from IP cores, contributing to unnecessary efficiency and energy degradation, are however revealed. So, to deal with this scenario, a Proffering Secure Energy-Aware Network-on-Chip (NoC) using Incremental Cryptogine is designed as the proposed work for the secure transmission of encrypted data and reducing the power and space consumption to enhance the performance. Unique NoC characteristics are implemented on the network interface for effectual lightweight encryption by Incremental Cryptogine to transmit encrypted data in a secured path. Aberrant Congestion Pattern Detection is used to identify the unusual traffic produced on the data transmission path. Spiking neural networks classifies the traffic and at the destination node, the encrypted data are decrypted into the original packet for secure data transmission. Cognizest Bipartite Buffer develops a unified buffer with the input ports on NoC and reduces an under-utilized buffer space by emphasizing an observation for the switch traversals to attain the competent performance for reducing both power and space consumption. Thus, better accuracy and performance in attack detection is achieved by using an incremental cryptogine to secure the data in Network-on-chip (NoC) thereby reducing both power and space consumption.

A Reliable Load Balancing Fault Tolerant Multi-SDN Controller approach in a typical Software Defined Network

INTRODUCTION: In the 21st Century, we have an emerging, modernized networking approach for efficient transfer of data in the form of packets i.e Software defined Networking (SDN). It is often recognized as the network paradigm acquired by an isolated independent control plane by the means of the underlying networking interface. As the communication medium is getting rapidly increased, the usage of the number of resources are also increasing in the same ratio, this results to connectivity problem in communication networks as well. If the development in technology is gaining more interest, the resource utilization will also increase.OBJECTIVES: In the proposed work here, we need to establish the connection between the client (or the end user) and the server by calculating the network performance using the parameters such as server response time and the throughput of the network by the method of load balancing.METHODS: This paper aims to identify the new methods or techniques to improve the performance of SDN with the increase in reliability, specifically required to improve the real-time data delivery. Alternatively, a reliable disjoint, distributed Multi- SDN controller will be used, to collect the updated network information like packet size, connectivity, packet flow etc. The methods involved are ideal controller optimization technique, distruption acquiscent technique and Maximum flow shortest route technique.RESULTS: From the results obtained by the simulation, the Reliable Load balancing Fault Tolerant Multi-SDN Controller(RLFTMS) approach is more reliable, fault tolerant compared to the other existing traditional mechanisms.CONCLUSION: Load balancing based on the server response time, throughput is being compared , this improves the server workload ditribution among various datacenters. Ultimately the customers or clients will have a great experience in terms of the reducing response time and increase in the throughput.

Multichannel Time Synchronization Based on PTP through a High Voltage Isolation Buffer Network Interface for Thick-GEM Detectors

Data logging and complex algorithm implementations acting on multichannel systems with independent devices require the use of time synchronization. In the case of Gas Electron Multipliers (GEM) and Thick-GEM (THGEM) detectors, the biasing potential can be generated at the detector level via DC to DC converters operating at floating voltage. In this case, high voltage isolation buffers may be used to allow communication between the different channels. However, their use add non-negligible delays in the transmission channel, complicating the synchronization. Implementation of a simplified precise time protocol is presented for handling the synchronization on the Field Programmable Gate Array (FPGA) side of a Xilinx SoC Zynq ZC7Z030. The synchronization is done through a high voltage isolated bidirectional network interface built on a custom board attached to a commercial CIAA_ACC carrier. The results of the synchronization are shown through oscilloscope captures measuring the time drift over long periods of time, achieving synchronization in the order of nanoseconds.