Interface Control Layer Research Articles

Exploration and Application of Software Development Automation Technology

Application development often faces problems such as demand changes, long cycle, and low efficiency. This paper attempts to solve such problems with automated generation technology. The article abstracts the design and development process of a typical application system; analyzes the key issues; then, after designing the overall architecture of the builder, it describes the design of interface presentation layer, control layer (business logic layer) and data model layer; finally this paper describes the challenges encountered by the builder and improvements in practice.

(Invited) MOS Interface Defect Control in Ge/III-V Gate Stacks

One of the most critical issues for realizing high performance Ge/III-V CMOS, which can be regarded as one of the promising device structures in the future technology nodes, is to establish the gate stack technologies simultaneously satisfying many requirements such as thin EOT, low interface state density (Dit), low slow trap density (Dtrap), high channel mobility and high gate insulator reliability. For this purpose, basic understanding of Ge/III-V MOS interfaces including physical origins of interface defects and the influence on channel mobility is indispensable. In order to realize low Dit, high channel mobility and thin EOT for Ge MOSFETs, we proposed an interfacial layer (IL) formation process employing ECR plasma post oxidation to form ultrathin GeOx through thin ALD Al2O3 [1, 2] or HfO2/Al2O3 [3]. By using the HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs (EOT of 0. 76 nm) with high electron (690 cm2/Vs) and hole (550 cm2/Vs) peak mobility were obtained. However, one of the most difficult challenges for the present GeOx-based ILs is the existence of high Dtrap [4, 5]. The slow traps can exist near GeOx/Ge interfaces, because the trapping characteristics are almost insensitive to the thickness of GeOx and Al2O3 [6]. Recently, inclusion of Y atoms into GeOx has been reported to effectively suppress Dtrap [7, 8]. We are currently working for the reduction in Dtrap by suing the ALD AlYO3/GeOx or Y2O3/GeOx interfaces [9, 10]. While the impact is still limited at present, further improvement in Dtrap is expected. For III-V MOS interface control, understanding of III-V MOS interface defects and establishment of the MOS interface defect control technologies have not been fully obtained yet. There still remain many issues, such as (1) higher Dit and Dtrap at InGaAs MOS gate stacks with Al2O3-based ILs than in Si and Ge MOS gate stacks (2) inferior MOS interface properties on Sb-based materials such as GaSb, GaAsSb and InGaSb (3) poor MOS gate stack reliability [5, 11, 12]. We studied the impact of ALD La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs. It was found that La2O3/InGaAs MOSFETs exhibit lower S. S. and lower carrier trapping properties, while have lower mobility than Al2O3/InGaAs MOSFETs because of higher fixed oxide charge density. Also, it was experimentally found that ALD La2O3 films with thermal budget lower than 300 oC have ferroelectricity in W/La2O3/InGaAs MOS and W/La2O3/W MIM structures. The steep slope characteristics due to the negative capacitance effect have been demonstrated in W/La2O3(15nm)/InGaAs MOSFETs [13]. We also found that BHF/HF pre-treatment is more effective for reduction of the fast interface state density at ALD Al2O3/InxGa1-xAs with higher In content (x=0.7 and 1) in comparison with conventional (NH4)Sy pre-treatment [14, 15]. It was suggested through the XPS analyses that the reduction in Dit is attributable to the dominance of As dangling bonds on Dit with higher In content and the effective passivation of oxygen atoms with these dangling bonds. For GaSb and GaAsSb MOS interface control, ultrathin InAs and InGaAs surface passivation layers have been found to be effective in reducing the fast interface state density [16, 17]. However, the detailed studies on further reduction in Dit and Dtrap and understanding of the relationship between the channel mobility and the interface properties are still strongly needed for Sb-based MOS devices. This work was partly supported by JST-CREST and the Grant in-Aid for Scientific Research through the MEXT (26249038). The authors would like to thank Drs. M. Yokoyama, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, and Drs. M. Mitsuhara, H. Sugiyama, T. Hoshi and H. Yokoyama in NTT for their collaborations.

Effect of Ge interface control layer on the interfacial and electrical properties of TaYOx thin films on GaAs substrates

Effects of a Ge interface control layer on the electrical properties of RF sputter-deposited TaYOx on n-GaAs substrates are studied in detail. It is found that the incorporation of an ultrathin Ge layer in between TaYOx and GaAs substrate improve various electrical parameters such as interface state density, border trap density, frequency dispersion, leakage current density and flat-band shift thereby improving capacitor performance. The trapping of charge carriers in GaAs MOS capacitors during constant voltage stress has also been studied and the increase in gate leakage current observed during electrical stress is estimated and explained by taking into account the build up of trap charges and stress induced trap generation. The cross-section of traps is also estimated to be in the range of 10ź18 cm2. Such a small value for the capture cross-section implies that the generated traps are neutral centers which are probably responsible for trap-assisted tunneling during voltage stressing.

(Invited) MOS Interface Control Technologies for Advanced III-V/ Ge Devices

One of the most critical issues for III-V/Ge MOSFETs, which have been regarded as a promising CMOS structure under sub 10 nm regime, is formation of superior gate stacks satisfying the requirements of thin EOT, excellent MOS interface quality enabling high channel mobility and low S factor and high reliability. As a result, MOS interface control engineering is still of paramount importance. In this presentation, we focus on viable III-V/Ge gate stack technologies by using ALD high-k films for realizing these requirements.Two types of III-V semiconductors, InGaAs- and GaSb-based materials, have currently stirred a strong interest for n- and p-MOSFETs, respectively. In addition, the GaSb-based materials have become important for tunnelling FET application. As for InGaAs gate stacks, the insertion of 0.2-nm-thick ultrathin Al2O3 inter-layer can effectively improve the HfO2/InGaAs interface properties, resulting in 1-nm-thick CET HfO2/Al2O3/InGaAs MOS gate stacks with low gate leakage of 2.4×10-2 A/cm2 [1]. The resent studies have revealed that ALD La2O3 gate stacks can yield lower Dit than the Al2O3 ones [2, 3], indicating that La2O3 can be a promising high k material for III-V gate stacks. On the other hand, we have found that the InGaAs gate stacks using La2O3 only can include a large amount of slow traps. We present that ultrathin La2O3 interface control layers combined with Al2O3 and HfO2 can optimize both fast interface state density and slow trap density near the MOS interfaces.As for GaSb gate stacks, much higher Dit of Al2O3/GaSb MOS interfaces than that of Al2O3/InGaAs MOS interfaces severely degrades the device performance. Any thermal processing significantly is observed to increase Dit at Al2O3/GaSb interfaces [4]. It is shown that InAs passivation can effectively improve the MOS interface properties and the thermal stability [5]. As a result, 2.5-nm-thick InAs passivation can provide the peak hole mobility of 159 cm2/Vs for Al2O3/InAs/GaSb pMOSFETs [6]. In addition, surface treatment for InAs/GaSb hetero-structures by buffered HF, instead of conventional (NH4)2Sx, can further improve Dit at the MOS interfaces with Al2O3 [7].As for Ge gate stacks, we have presented ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks, fabricated by a plasma post oxidation method [8, 9]. HfO2/Al2O3/GeOx/Ge gate stacks with EOT of 0.76 nm have yielded (100) Ge p- and n-MOSFETs with high peak mobility of 546 cm2/Vs and 690 cm2/Vs, respectively [9]. We evaluated limiting factors of electron and hole mobility in Ge n- and p-MOSFETs. In a high Ns region the Ge MOS channel mobility is significantly degraded by surface roughness scattering as well as trapping of free electrons and holes into interface states inside the conduction and valence bands [10, 11]. The mobility in the high Ns region can be improved by reduction in surface roughness through a layer-by-layer plasma oxidation process [10]. Also, atomic Deuterium annealing can reduce Dit inside the bands, resulting in higher effective mobility [12]. However, the decrease in slow trap density for the Ge MOS gate stacks is a strong concern. While we observed the decrease in slow trap density near the valence band edge of Ge for ALD AlYO3/GeOx/Ge gate stacks formed by plasms post oxidation [13], the reduction in slow trap density for n-MOSFETs has not been obtained yet. Further optimization of Ge gate stacks is strongly needed for obtaining sufficient reliability in Ge CMOS.This work was partly supported by JST-CREST, the Grant in-Aid for Scientific Research through the MEXT (26249038), and the Innovation Research Project on Nano electronics Materials and Structures from NEDO. The authors would like to thank Drs. H. Yamada and O. Ichikawa in Sumitomo Chemical Corporation, and Drs. H. Yokoyama and M. Mitsuhara in NTT for their collaborations.

Modulating the interface quality and electrical properties of HfTiO/InGaAs gate stack by atomic-layer-deposition-derived Al₂O₃ passivation layer.

In current work, the effect of the growth cycles of atomic-layer-deposition (ALD) derived ultrathin Al2O3 interfacial passivation layer on the interface chemistry and electrical properties of MOS capacitors based on sputtering-derived HfTiO as gate dielectric on InGaAs substrate. Significant suppression of formation of Ga-O and As-O bond from InGaAs surface after deposition of ALD Al2O3 with growth cycles of 20 has been achieved. X-ray photoelectron spectroscopy (XPS) measurements have confirmed that suppressing the formation of interfacial layer at HfTiO/InGaAs interface can be achieved by introducing the Al2O3 interface passivation layer. Meanwhile, increased conduction band offset and reduced valence band offset have been observed for HfTiO/Al2O3/InGaAs gate stack. Electrical measurements of MOS capacitor with HfTiO/Al2O3/InGaAs gate stacks with dielectric thickness of ∼4 nm indicate improved electrical performance. A low interface-state density of (∼1.9) × 10(12) eV(-1) cm(-2) with low frequency dispersion ( ∼ 3.52%), small border trap density of 2.6 × 10(12) cm(-2), and low leakage current of 1.17 × 10(-5) A/cm(2) at applied gate voltage of 1 V have been obtained. The involved leakage current conduction mechanisms for metal-oxide-semiconductor (MOS) capacitor devices with and without Al2O3 interface control layer also have been discussed in detail.

Interface properties, physical and electrical characterization of sputtered TaAlO x on silicon-passivated n-GaAs substrates

In this paper, we present the interfacial and electrical properties of GaAs MOS capacitors fabricated using RF-sputtered TaAlO x dielectrics with and without a silicon interface control layer (ICL). As-deposited films are analyzed by X-ray photoelectron spectroscopy, which reveals that the suppression of low-k (Ga-O and As-O) interfacial layer formation is achieved with the introduction of an ultra-thin Si ICL. Silicon-passivated GaAs MOS capacitors exhibit excellent electrical properties featuring low hysteresis of 0.2 V and minimum interface-trapped charge density D it of 3.1 × 1012 eV−1 cm−2. The TaAlO x /Si/n-GaAs stack shows very low-frequency dispersion (~2.8 %), which is attributed to the reduction of interfacial oxides (Ga-O and As-O) and thus unpins the Fermi level. The current density of 5.1 × 10−5 A cm−2 at 1 V with an EOT of 2.4 nm is achieved in GaAs MOS capacitors with the introduction of a Si ICL. Furthermore, the electrical conduction mechanisms of TaAlO x thin films are also investigated as a function of temperature. Our findings unveil that the introduction of a silicon inter-layer between TaAlO x and GaAs becomes an effective way to improve interfacial and electrical characteristics of the MOS capacitor.

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlO x on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage ( C– V) and current voltage ( I– V) characteristics for GaAs/Si/HfAlO x and GaAs/HfAlO x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C– V and I– V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t bd ⩾ 1350 s) is observed for HfAlO x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.

Electrical analysis of three-stage passivated In0.53Ga0.47As capacitors with varying HfO2 thicknesses and incorporating an Al2O3 interface control layer

The atomic layer deposition of high dielectric constant oxides like HfO2 on III-V substrates such as In0.53Ga0.47As leads to a poor interface, with the growth of In0.53Ga0.47As native oxides regardless of the surface pretreatment and passivation method. The presence of the native oxides leads to poor gate leakage current characteristics due to the low band gap of the native oxides and the presence of potential wells at the interface. In addition, the poor quality of this interface leads to very large interface state defect densities, which are detrimental to metal-oxide-semiconductor-based device performance. A wide band gap interlayer replacing the native oxide layer would remove the potential wells and provide a larger barrier to conduction. It may also assist in the improvement of the interface quality, but the problem remains as to how this native oxide interlayer cannot only be removed but prevented from regrowing. In this regard, the authors present electrical results showing that the atomic layer deposition (ALD) growth of a thin (∼1 nm) Al2O3 layer before the ALD growth of HfO2 causes a removal/reduction of the native oxides on the surface by a self-cleaning process without subsequent regrowth of the native oxides. As a result, there are significant improvements in gate leakage current densities, and significant improvements in the frequency dispersion of capacitance versus gate voltage, even when a defective In0.53Ga0.47As epitaxial layer on an InP substrate is employed. Measurements at different temperatures confirm that the frequency dispersion is mainly due to interface state defect responses and another weakly temperature dependent mechanism such as border traps, after accounting for the effects of nonideal In0.53Ga0.47As epitaxial layer growth defects where applicable.

Structural and Electrical Analysis of Thin Interface Control Layers of MgO or Al2O3 Deposited by Atomic Layer Deposition and Incorporated at the High-k/III-V Interface of MO2/InxGa1-xAs (M = Hf|Zr, x = 0|0.53) Gate Stacks

Control of the high-k/III-V interface by deposition of thin (~1-2 nm) interface control layers (ICLs) of Al2O3 or MgO, as part of an overall bi-layer structure with a high-k metal oxide MO2 (M = Hf|Zr), is explored. An Al2O3 or MgO ICL is deposited on unpassivated InxGa1-xAs (x = 0|0.53) substrates prior to MO2 gate oxide deposition, forming a Pd/high-k/ICL/III-V gate stack. The aim of a bi-layer structure is to enable continued device scaling using a high-k MO2 oxide while improving the high-k/III-V interface quality and interfacial band structure, with an Al2O3 or MgO ICL. Metal-oxide-semiconductor capacitor (MOSCAP) devices with an Al2O3 ICL on p-GaAs display significantly reduced leakage current density, and reduced frequency dispersion of accumulation capacitance when compared to a no-ICL device, indicating an improved high-k/III-V band structure and interface quality, respectively. Further studies on ZrO2/Al2O3/In0.53Ga0.47As devices find a reduced defect response with a post-metal forming gas anneal.

Structural and electrical analysis of the atomic layer deposition of HfO2/n-In0.53Ga0.47As capacitors with and without an Al2O3 interface control layer

High mobility III-V substrates with high-k oxides are required for device scaling without loss of channel mobility. Interest has focused on the self-cleaning effect on selected III-V substrates during atomic layer deposition of Al2O3. A thin (∼1 nm) Al2O3 interface control layer is deposited on In0.53Ga0.47As prior to HfO2 growth, providing the benefit of self-cleaning and improving the interface quality by reducing interface state defect densities by ∼50% while maintaining scaling trends. Significant reductions in leakage current density and increased breakdown voltage are found, indicative of a band structure improvement due to the reduction/removal of the In0.53Ga0.47As native oxides.

Charge trapping and reliability characteristics of ultra-thin HfYO x films on n-GaAs substrates

Ultra-thin layers of the HfYO x gate dielectric were deposited on n-GaAs substrates by employing radio frequency (rf) sputter deposition system with a Si interface control layer sandwiched between the dielectric and semiconductor. The trapping/detrapping behaviour of charge carriers in the ultra-thin HfYO x /Si gate dielectric stack has been extensively studied during constant-voltage stressing (CVS) and compared with the results obtained from directly deposited HfYO x films on n-GaAs. The increase in gate leakage current observed during electrical stress is estimated and explained by taking into account the build up of trap charges and stress induced trap generation. Also, the capture cross-section of the generated traps is estimated. The variation of the trap centroid and the trapped charge density with injected influences have been investigated using constant current stressing (CCS) measurements. The dielectric breakdown and reliability of the dielectric films have been studied using constant-voltage stressing. A high time-dependent dielectric breakdown (TDDB, t bd ⩾ 1700 s) is observed for HfYO x gate dielectric with a silicon inter-layer under a high constant-voltage stress (8 V).

Structural and Electrical Analysis of Thin Interface Control Layer Effects of MgO or Al2O3 Deposited by Atomic Layer Deposition, Incorporated at the High-k/IIIV Interface of MO2/InxGa1-xAs (M = Hf|Zr, x = 0|0.53) Gate in Metal-Oxide-Semiconductor Capacitors

not Available.

Improved electrical and interfacial properties of RF-sputtered HfAlO x on n-GaAs with effective Si passivation

In this paper, we present the effects of ultrathin Si interfacial layer on the physical and electrical properties of GaAs MOS capacitors fabricated using RF-sputtered HfAlO x gate dielectric. It is found that HfAlO x /Si/n-GaAs stack exhibits excellent electrical properties with low frequency dispersion (∼4.8%), hysteresis voltage (0.27 V) and interface trap density (1.3 × 10 12 eV −1 cm −2). The current density of 3.7 × 10 −5 A/cm 2 is achieved with an equivalent-oxide-thickness of 1.8 nm at V FB + 1 V for Si-passivated HfAlO x films on n-GaAs. X-ray photoelectron spectroscopy (XPS) analysis shows that the suppression of low-k interfacial layer formation is accomplished with the introduction of ultrathin Si interface control layer (ICL). Thus the introduction of thin layer of Si between HfAlO x dielectrics and GaAs substrate is an effective way to improve the interface quality such as low frequency dispersion, hysteresis voltage and leakage current. Additionally, current conduction mechanism has been studied and the dominant conduction mechanisms are found to be Schottky emission at low to medium electric fields and Poole–Frenkel at high fields and high temperatures under substrate injection. In case of gate injection, the main current conduction at low field is found to be the Schottky emission at high temperatures.

(Invited) Investigation of High-κ/InxGa1-xAs Interfaces

The quality of the high-k/InxGa1-xAs interface is a crucial factor in achieving high electron mobility compound semiconductor field effect transistors. Capacitance and conductance characterisation methods were employed to evaluate different high-k/InGaAs interfaces. This paper will first discuss the specificity of capacitance voltage characteristics of compound semiconductor MOS structures, and then the recent progress in the study of high k/InxGa1 xAs interfaces will be presented. The capacitance and conductance measurements are combined to provide a picture of the interface state density. We have also investigated the merit of using intermediate k value dielectrics such as Al2O3 and MgO as interface control layers between the semiconductor and the main high k layer.

Surface passivation of III–V semiconductors for future CMOS devices—Past research, present status and key issues for future

Currently, III–V metal–insulator–semiconductor field effect transistors (MISFETs) are considered to be promising device candidates for the so-called “More Moore Approach” to continue scaling CMOS transistors on the silicon platform. Strong interest also exists in III–V nanowire MISFETs as a possible candidate for a “Beyond CMOS”-type device. III–V sensors using insulator–semiconductor interfaces are good candidates for “More Moore”-type of devices on the Si platform. The success of these new approaches for future electronics depends on the availability of a surface passivation technology which can realize pinning-free, high-quality interfaces between insulator and III–V semiconductors. This paper reviews the past history, present status and key issues of the research on the surface passivation technology for III–V semiconductors. First, a brief survey of previous research on surface passivation and MISFETs is made, and Fermi level pinning at insulator–semiconductor interface is discussed. Then, a brief review is made on recent approaches of interface control for high-k III–V MIS structures. Subsequently, as an actual example of interface control, latest results on the authors’ surface passivation approach using a silicon interface control layer (Si ICL) are discussed. Finally, a photoluminescence (PL) method to characterize the interface quality is presented as an efficient contactless and non-destructive method which can be applied at each step of interface formation process without fabrication of MIS capacitors and MISFETs.

High-k Al 2O 3 MOS structures with Si interface control layer formed on air-exposed GaAs and InGaAs wafers

This paper attempts to realize unpinned high-k insulator–semiconductor interfaces on air-exposed GaAs and In 0.53Ga 0.47As by using the Si interface control layer (Si ICL). Al 2O 3 was deposited by ex situ atomic layer deposition (ALD) as the high-k insulator. By applying an optimal chemical treatment using HF acid combined with subsequent thermal cleaning below 500 °C in UHV, interface bonding configurations similar to those by in situ UHV process were achieved both for GaAs and InGaAs after MBE growth of the Si ICL with no trace of residual native oxide components. As compared with the MIS structures without Si ICL, insertion of Si ICL improved the electrical interface quality, a great deal both for GaAs and InGaAs, reducing frequency dispersion of capacitance, hysteresis effects and interface state density ( D it). A minimum value of D it of 2 × 10 11 eV −1 cm −2 was achieved both for GaAs and InGaAs. However, the range of bias-induced surface potential excursion within the band gap was different, making formation of electron layer by surface inversion possible in InGaAs, but not possible in GaAs. The difference was explained by the disorder induced gap state (DIGS) model.

Control of interface between HfO2 and air‐exposed InGaAs by ultrathin Si interface control layer

AbstractThis paper attempts to control the interface between the air‐exposed InGaAs wafer and a high‐k dielectric by the Si interface control layer (ICL) technique. As the high‐k insulator, HfO2 film was formed by atomic layer deposition (ALD). Prior to a molecular beam epitaxy (MBE) growth of the Si ICL, efforts were made to minimize native oxide components from the InGaAs surface by various wet surface treatment. After the growth of the Si ICL, an ultrathin SiNx layer was formed by in‐situ partial nitridation of the Si ICL to prevent a subcutaneous oxidation during the sample transfer in air to the ALD chamber. Surface/interface properties were characterized by in‐situ X‐ray photoelectron spectroscopy (XPS) at each step of interface formation. By using HF‐based cleaning, interface bonding configurations similar to those obtained by in‐situ UHV process was realized with no trace of native oxide components. As compared with the ALD HfO2/InGaAs metal‐insulator‐semiconductor (MIS) structure which showed existence of strong Fermi level pinning, insertion of the Si ICL achieved large reduction of interface state density, Dit, giving a minimum value of 2x1011 eV‐1cm‐2. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Effects of an ultrathin Si passivation layer on the interfacial properties of RF-sputtered HfYOx on n-GaAs substrates

In this paper, we present the results of our investigations on the effects of an ultrathin Si interface control layer on the electrical properties of MOS capacitors fabricated using RF-sputtered HfYOx as the dielectric on n-GaAs. X-ray photoelectron spectroscopy analysis shows that suppression of low-k interfacial layer formation is accomplished with the introduction of an ultrathin Si interface control layer. I–V and C–V characteristics of Al/HfYOx/Si/n-GaAs MOS capacitors with an effective dielectric thickness of ∼1.8 nm show superior electrical properties. A density Dit of (1–2) × 1012 eV−1 cm−2 of low mid-gap interface states with low frequency dispersion (<3.3%) and a low border trap density of 1.7 × 1012 cm−2 have been obtained.

Capacitance-voltage and photoluminescence study of high-k∕GaAs interfaces controlled by Si interface control layer

The authors performed a detailed capacitance-voltage (C-V) and photoluminescence (PL) study of the high-k dielectric/GaAs interface controlled by the Si interface control layer (Si ICL) grown by molecular beam epitaxy to investigate the feasibility of a PL method for interface characterization and to find out the optimum thickness of the Si ICL. The sample had a HfO2∕SiNx∕Si ICL/n-GaAs structure where the ultrathin SiNx buffer layer was formed by in situ partial nitridation of the Si ICL itself. For this structure, they measured the quantum efficiency of photoluminescence as a function of the excitation photon flux density and carried out a computer analysis to determine the most likely distribution of the interface state density Dit. Remarkably good agreements were obtained between the high-frequency C-V method and the PL method, indicating that the present PL method may serve as a powerful contactless and nondestructive tool for developing an optimal surface passivation structure and its processing technology. Using C-V and PL methods, they found the optimum initial thickness of Si ICL before partial nitridation to be 5–6 ML. With this thickness, a Dit minimum value of (1–2)×1011cm−2eV−1 was achieved in the HfO2∕SiNx∕Si ICL/n-GaAs structure. When the thickness was too large, it led to the generation of misfit dislocations, whereas a too thin Si ICL led to subcutaneous nitridation of GaAs during partial nitridation of the Si ICL, leading to interface disorder.

Optimization of Si interface control layer thickness for high- k GaAs metal–insulator–semiconductor structures

This paper reports on a GaAs high- k MIS structure having an MBE-grown Si interface control layer (ICL) which has recently shown a promising result. It has a HfO 2/SiN x /Si ICL/GaAs structure where an ultrathin SiN x buffer layer is produced by direct nitridation of Si ICL. In this study, a particular attention is paid to optimize the initial thickness of Si ICL by correlating the interface structure studied by in situ X-ray photoelectron spectroscopy with the electronic interface quality studied by capacitance–voltage measurements. It was found that the presence of ML-level Si ICL at the interface after the formation of the SiN x is vitally important to obtain low values of interface trap density ( D it). Excess initial thickness of Si ICL also resulted in increase of D it. Initial Si ICL thicknesses of 5–6 MLs were found to be optimum, and gave U-shaped D it distributions with minimum D it values around 1 × 10 11 cm −2 eV −1 or below.