Interconnection Yield Research Articles

Energy Yield Prediction of Offshore Wind Farm Clusters at the EERA-DTOC European Project

A new integrated design tool for optimization of offshore wind farm clusters is under development in the European Energy Research Alliance – Design Tools for Offshore wind farm Cluster project (EERA DTOC). The project builds on already established design tools from the project partners and possibly third-party models. Wake models have been benchmarked on the Horns Rev and, currently, on the Lilgrund wind farm test cases. Dedicated experiments from ‘BARD Offshore 1’ wind farm will using scanning lidars will produce new data for the validation of wake models. Furthermore, the project includes power plant interconnection and energy yield models all interrelated with a simplified cost model for the evaluation of layout scenarios. The overall aim is to produce an efficient, easy to use and flexible tool - to facilitate the optimised design of individual and clusters of offshore wind farms. A demonstration phase at the end of the project will assess the value of the integrated design tool with the help of potential end-users from industry.This abstracts summarizes the objectives and preliminary results of work package 3. In order to provide an accurate value of the expected net energy yield, the offshore wind resource assessment process has been reviewed as well as the sources of uncertainty associated to each step. Methodologies for the assessment of offshore gross annual energy production are analyzed based on the Fino 1 test case. Measured data and virtual data from Numerical Weather Prediction models have been used to calculate long term wind speed, wind profile and gross energy.

Technological and Electrical Performances of Ultrafine-Pitch Flip-Chip Assembly Based on Room-Temperature Vertical Interconnection

Flip-chip is a high-density and highly reliable interconnection technology, which is widely used for the fabrication of infrared complementary metal-oxide-semiconductor imagers. In order to increase the format and the resolution of staring arrays to 2000 × 2000 pixels or even larger complexities, while keeping substrate dimensions and device cost low, there is a general trend in reducing pixel size. But this results in a very challenging process control for ultrafine-pitch and high-count flip-chip bonding technology. A new room-temperature insertion technology has been proposed and developed to alleviate most of these issues. It overcomes the planarity and thermal mismatch issues of this heterogeneous assembly made of cadmium mercury telluride detectors hybridized on silicon read-out circuits while reducing the bonding thermocompression forces and the hybridization temperature. The technological preparation of the assembled devices is described in this paper. A process characterization, using a modified nanoindenter with instrumentation for single tip insertion, has been achieved to evaluate insertion mechanical parameters. This paper gives also the first measured interconnection yield and vertical access resistance of 2000 × 2000 hybridized arrays of 10 μm pitch, fabricated using the proposed insertion flip-chip technique. Connection results are discussed, and a comparative study proves that parallelism during insertion is a key parameter. When providing a perfect parallelism control with advanced new flip-chip bonders, the microtip insertion technique is scalable to complexities of over 4 million connections at very fine pitch. Moreover, this new low-temperature insertion concept could possibly be applied to 3-D interstrata interconnections for electronic devices. Indeed, it avoids the issues caused by cumulative high-temperature cycles, which are typical of more conventional processes.

Cost effective flip chip assembly and interconnection technologies for large area pixel sensor applications

Much of the cost of manufacturing pixel detectors is due to bumping and flip chip assembly of the readout chips onto sensor tiles, even if it is done on wafer level. To address this issue, Fraunhofer IZM investigated two new technological approaches, namely screen printing using dry film resist and chip-to-wafer assembly. In the first approach, solder bumps with diameters of 80 and 25 μm in pitches of 110 and 60 μm, respectively, were produced by screen-printing solder paste using a photo-structured dry film resist. Results indicated that the technology is a viable high yield and low cost bumping process. The second approach was developed to decrease the number of manual handling steps in pixel module manufacturing, which is critical for reducing processing time and cost. Here, chip designs on 200 mm readout chip (ROC) wafers and 150 mm sensor wafers were especially adapted for chip-to-wafer assembly and to ensure that the interconnection yield and reliability could be tested. After bumping and dicing of the readout chip wafer and UBM plating on the sensor wafer, individual dice were flip chip mounted on the pre-diced sensor wafer. This paper describes the technological steps, key processing parameters and first results for both technologies.

Dense Intra-Cavity Interconnection Technology for Hermetically Packaged MMICs

Northrop Grumman Space Technology has recently developed a technology that is capable of creating dense intra- cavity interconnections (ICICs) for hermetically packaged MMICs. These interconnections provide signal routing between circuits residing on the facing surfaces within the sealed wafer level package. They are fabricated by batch processes and are fully compatible with NGST's MMIC production processes. Greater than 90% interconnection yield is consistently obtained from different substrate material combinations. RF ICIC transitions with insertion loss of less than 0.1dB at 15GHz have been demonstrated. These ICICs are also proven to be mechanically and thermally robust. NGST's dense ICIC technology enables heterogeneous integration of multi-functional MMICs and MMIC modules.

Accommodative competitive entry policies and telecommunications regulation

Accommodative competitive entry policies (unbundling, resale and interconnection) yield contestable retail telecommunications markets. The combination of setting efficient prices for network elements and allowing competitors to choose their preferred level of wholesale quality renders the retail market self‐regulating with respect to both price and quality. Any overhang of regulation at the retail level under these conditions is potentially harmful to fostering a competitive market outcome.

Quality enhancement of reconfigurable multichip module systems by redundancy utilization

This paper evaluates the quality effectiveness of redundancy utilization in reconfigurable multichip mode (RMCM) systems. Due to reconfigurability, the RMCM system can implement a device with different redundancy levels. A redundancy level is determined by the requirement of fault tolerance (FT) of the device under implementation which can be realized through reconfiguration. No previous work has adequately investigated the effect of utilization of redundancy on the quality-level (QL) of RMCM. In this paper, the tolerance to escape from testing is also introduced to provide more extensive and comprehensive analysis and is referred to as escape tolerance (ET). This can be achieved by utilizing an appropriate amount of redundancy and is exploited for evaluating its effect on the QL of RMCM with different utilizations of redundancy. It is shown through theoretical analysis that the coverage of testing [i.e., fault coverage (FC)] can be improved by reconfiguration. Thus, we derive the QL by relating the QL to the yield enhancement by reconfiguration, the effect of interconnection yield and ET on the QL, and the improvement in FC by reconfiguration. In the proposed approaches, appropriate combinatorial models are formulated to take into account the parameters related to the redundancy and reconfiguration process in RMCM systems. From the extensive parametric simulation results, it is shown that there exists a bound in the effectiveness of redundancy utilization (i.e., the amount of redundancy) depending on the RMCM yield and FC. Using the proposed approach, the redundancy utilization in RMCM systems can be appropriately used to enhance the QL.

Extended-wavelength InGaAs-on-GaAs infrared focal-plane array

A 320×256 element hybrid infrared array is presented which consists of In0.78Ga0.22As photodiodes grown by molecular beam epitaxy on a GaAs substrate. The interconnection yield of the hybrid indium-bump process is above 97%. Electro-optical sensor characteristics are discussed.

Factors affecting the interconnection resistance and yield in multilayer polyimide—copper structures

Factors affecting the interconnection resistance and yield in multilayer polyimide—copper structures

Factors affecting the interconnection resistance and yield in multilayer polyimide/copper structures

The use of a lift-off technique to fabricate a high-density structure consisting of multiple layers of metal/polyimide thin-film structures on a silicon substrate is described. To achieve better performance and high yield, the process design, the processing parameters, the thickness of the Cr/Cu/Cr metallurgy, and the use of suitable polyimide dielectrics, were evaluated. The plasma processing conditions, the types of passivation metals on Cu, and the use of a siloxane-polyimide as the gap-fill/etch-stop material were all shown to play a critical role in affecting the interconnection resistance and yield of the multilayer thin-film structures. By optimizing these parameters the feasibility of fabricating high-density thin-film wiring layers with good yield is demonstrated. >

Molybdenum Taper Dry Etching

A taper dry etching technique for molybdenum films is proposed. The dry etching characteristics of oxygen‐doped Mo films in a discharge are studied. It is found that oxygen‐doped Mo films are etched at a higher rate than oxygen‐undoped Mo film and that, in oxygen‐doped Mo films, undercutting occurs differently from oxygen‐undoped Mo film. Making use of the Mo etching characteristics, tapered Mo patterns with little linewidth loss to resist patterns are obtained by plasma etching of the Mo double layer, namely an oxygen‐doped Mo film over an oxygen‐undoped Mo film. The taper angle is varied from 40° to 60° by varying the thickness ratio of the oxygen‐doped Mo film to the total Mo double layer. This technique promises to improve an interconnection yield in LSI's through reduction of wiring disconnection or shorts over the tapered‐Mo steps.