Interconnection Networks For Parallel Computers Research Articles

A Descriptive Study on Interconnection Networks for Parallel Computing and Algorithm Models in Parallel Computing

In parallel computing, Interconnection networks are very crucial for efficient communication among all processors within a similar system. Parallel computing has become a crucial topic in the concern of computer science and also it is revealed to be critical when researching in high performance. The evolution of computer architectures towards an improved number of nodes, where parallelism could be the approach to option for speeding up an algorithm within the last few decades. Efficient data transfer between processors is an essential component in any large scale parallel computation. Motivated by the growing interest in parallel computers, a significant amount of theoretical research has been devoted to the area of interconnection networks for parallel computers, most of it to the packet routing (or store-and-forward) model of communication. We survey some of the major developments in this field, and discuss several new alternative models of communication, In many large scale applications, communication time dominates the execution time of the whole parallel computation. Thus, the performance of a large scale parallel computer is highly correlated with the efficiency of its network and communication algorithm. The combination of processing units build a model of computation (circuits) has gained an essential place in the area of high performance computing (HPC) due to its configuration and considerable processing supremacy that is parallel, series, etc. The aim of the Presenting this paper is study on the idea of parallel computing and its programming models and also explore some theoretical and technical concepts which can be often needed to understand the Interconnection network. In particular, we show how this technology is new in assisting the field of computational physics, especially when the issue is data parallel. In the real-life example of parallel computing, there are two queues to get a ticket of anything; if two cashiers are giving tickets to 2 persons simultaneously, it helps to save time as well as reduce complexity

Symmetric property and reliability of locally twisted cubes

The locally twisted cube LTQn is a variant of the hypercube Qn, which was introduced by Yang et al. (2005) as an interconnection network for parallel computing. The symmetry of Qn is well-known, for example, it is an edge-transitive Cayley graph. However, the symmetry of LTQn remains unclear. In this paper, we first prove that LTQn with n≥4 is isomorphic to a bi-Cayley graph of an elementary abelian 2-group Z2n−1 of order 2n−1, and then prove that the full automorphism group of LTQn with n≥4 is isomorphic to Z2n−1. These show that LTQn with n≥4 is not edge-transitive, and its full automorphism group has exactly two orbits on the vertex set of LTQn (and consequently it is not vertex-transitive and not a Cayley graph). What is more, the symmetry of LTQn with n≥4 also implies that it can be decomposed to two vertex-disjoint (n−1)-dimensional hypercubes and a perfect matching. As an application, we obtain the k-extra connectivity and (k+1)-component connectivity with k≤n−1 of LTQn, which generalize some previous works.

A New Record of Graph Enumeration Enabled by Parallel Processing

Using three supercomputers, we broke a record set in 2011, in the enumeration of non-isomorphic regular graphs by expanding the sequence of A006820 in the Online Encyclopedia of Integer Sequences (OEIS), to achieve the number for 4-regular graphs of order 23 as 429,668,180,677,439, while discovering several regular graphs with minimum average shortest path lengths (ASPL) that can be used as interconnection networks for parallel computers. The enumeration of 4-regular graphs and the discovery of minimal-ASPL graphs are extremely time consuming. We accomplish them by adapting GENREG, a classical regular graph generator, to three supercomputers with thousands of processor cores.

Hardware design of parallel switch setting algorithm for Benes networks

Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system, and networks-on-chip. The parallel switch setting algorithm is the key to satisfy the requirements of high performance switching networks. The Lee's routing algorithm is by far the most efficient parallel routing algorithm for Benes networks. However, there is no hardware implementation for this algorithm. In this paper, the Lee's routing algorithm is fully implemented in RTL and synthesised. We have refined the algorithm in data structure and initialisation/updating of relation values to make it suitable for hardware implementation. The simulation and synthesis results of the switching setting circuits for 4 × 4 to 64 × 64 Benes networks confirm that the timing, area, and power consumption of the circuit is consistent with the complexity of the Lee's algorithm. To the best of our knowledge, this is the first complete hardware implementation of the parallel switch setting algorithm which can handle all types of permutations including partial ones.

Hardware design of parallel switch setting algorithm for Benes networks

Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system, and networks-on-chip. The parallel switch setting algorithm is the key to satisfy the requirements of high performance switching networks. The Lee's routing algorithm is by far the most efficient parallel routing algorithm for Benes networks. However, there is no hardware implementation for this algorithm. In this paper, the Lee's routing algorithm is fully implemented in RTL and synthesised. We have refined the algorithm in data structure and initialisation/updating of relation values to make it suitable for hardware implementation. The simulation and synthesis results of the switching setting circuits for 4 × 4 to 64 × 64 Benes networks confirm that the timing, area, and power consumption of the circuit is consistent with the complexity of the Lee's algorithm. To the best of our knowledge, this is the first complete hardware implementation of the parallel switch setting algorithm which can handle all types of permutations including partial ones.

Formula omitted]-restricted connectivity of locally twisted cubes

Given a graph G and a non-negative integer h, the h-restricted connectivity of G, denoted by κh(G), is defined as the minimum size of a set X of nodes in G (X⊂V(G)) such that G−X is disconnected, and the degree of each component in G−X is at least h. The h-restricted connectivity measure is a generalization of the traditional connectivity measure, and it improves the connectivity measurement accuracy. Moreover, studies have revealed that if a network possesses a restricted connectivity property, it is more reliable and demonstrates a lower node failure rate compared with other networks. The n-dimensional locally twisted cube LTQn, which is a well-known interconnection network for parallel computing, is a variant of the hypercube Qn. Most studies have examined the h-restricted connectivity of networks under the conditions of h=1 or h=2. This paper examines a generalized h-restricted connectivity measure for n-dimensional locally twisted cube and reveals that κh(LTQn)=2h(n−h) for 0≤h≤n−2.

Hamiltonian cycle in k-ary 2-cube

The k-ary n-cube has been one of the most popular interconnection networks for parallel computing. In this paper, we assume that k⩾4 is an even. Under this assumption we investigate the Hamiltonian cycle of k-ary 2-cube with the set F of faulty elements (vertices and/or edges), and will prove that k-ary 2-cube is 2-fault bi-Hamiltonian.

Embedding of Binomial Trees in Locally Twisted Cubes with Link Faults

As a newly introduced interconnection network for parallel computing, the locally twisted cube possesses many desirable properties. In this paper, binomial tree embeddings in locally twisted cubes are studied. We present two major results in this paper: (1) For any integern≥ 2, ann-dimensional binomial treeBncan be embedded inLTQnwith dilation 1 by randomly choosing any vertex inLTQnas the root. (2) For any integern≥ 2, ann-dimensional binomial treeBncan be embedded inLTQnwith up ton− 1 faulty links inlog(n− 1) steps where dilation = 1. The results are optimal in the sense that the dilations of all embeddings are 1.

Panconnectivity and pancyclicity of the 3-ary n-cube network under the path restrictions

The k-ary n-cube, denoted by Qnk, is one of the most important interconnection networks for parallel computing. In this paper, we consider the problem of embedding paths and cycles into 3-ary n-cubes under the path restrictions. Let P be a path in Qn3. We show that when |V(P)|⩽2n-3, there exists a path of any length from n+1 to |V(Qn3-P)|-1 between two arbitrary nodes in Qn3-P. We also prove that when |E(P)|⩽2n-1, there exists a cycle of any length from |E(P)|+n to |V(Qn3)| in Qn3 passing through P. Our results are best possible in some sense.

Largest Connected Component of a k-ary n-cube with Faulty Vertices *

The k-ary n-cube is one of the most popular interconnection networks for parallel computing. This paper addresses the size of a largest connected component of a faulty k-ary n-cube. We prove that, in a k-ary n-cube (k ≥ 4 and n ≥ 2) with up to 4n-2 faulty vertices, all fault-free vertices but at most two constitute a connected component. Moreover, this assertion holds if and only if the set of all faulty vertices is equal to the neighborhood of a pair of fault-free adjacent vertices.

Embedding Complete Binary Trees into Locally Twisted Cubes

The locally twisted cube is a newly introduced interconnection network for parallel computing, which possesses many desirable properties. In this paper, the problem of embedding complete binary trees into locally twisted cubes is studied.Let LTQn(V;E) denote the n-dimensional locally twisted cube.We find the following result in this paper: for any integern ≥ 2,we show that a complete binary tree with 2n—1 nodes can be embedded into the LTQn with dilation 2.

Fault-tolerant embedding of meshes/tori in twisted cubes

Twisted cubes are an important class of hypercube-variant interconnection networks for parallel computing. In this paper, we evaluate the fault-tolerant mesh/torus embedding abilities of twisted cubes. By reducing the fault-tolerant mesh/torus embedding problem to the fault-tolerant pancyclicity, we propose several schemes for embedding meshes/tori in faulty twisted cubes. The obtained results reveal another appealing fault-tolerant feature of twisted cubes.

Embedding meshes into locally twisted cubes

As a newly introduced interconnection network for parallel computing, the locally twisted cube possesses many desirable properties. In this paper, mesh embeddings in locally twisted cubes are studied. Let LTQ n ( V, E) denote the n-dimensional locally twisted cube. We present three major results in this paper: (1) For any integer n ⩾ 1, a 2 × 2 n−1 mesh can be embedded in LTQ n with dilation 1 and expansion 1. (2) For any integer n ⩾ 4, two node-disjoint 4 × 2 n−3 meshes can be embedded in LTQ n with dilation 1 and expansion 2. (3) For any integer n ⩾ 3, a 4 × (2 n−2 − 1) mesh can be embedded in LTQ n with dilation 2. The first two results are optimal in the sense that the dilations of all embeddings are 1. The embedding of the 2 × 2 n−1 mesh is also optimal in terms of expansion. We also present the analysis of 2 p × 2 q mesh embedding in locally twisted cubes.

Fault-tolerant meshes and tori embedded in a faulty supercube

Hypercubes, meshes, and tori are well known interconnection networks for parallel computing. The Supercube network is a generalization of the hypercube. The main advantage of this network is that i...

Embedding paths and cycles in 3-ary n-cubes with faulty nodes and links

The k-ary n-cube, denoted by Q n k , is one of the most important interconnection networks for parallel computing. In this paper, we consider the problem of embedding cycles and paths into faulty 3-ary n-cubes. Let F be a set of faulty nodes and/or edges, and n ⩾ 2 . We show that when | F | ⩽ 2 n - 2 , there exists a cycle of any length from 3 to | V ( Q n 3 - F ) | in Q n 3 - F . We also prove that when | F | ⩽ 2 n - 3 , there exists a path of any length from 2 n - 1 to | V ( Q n 3 - F ) | - 1 between two arbitrary nodes in Q n 3 - F . Since the k-ary n-cube is regular of degree 2 n , the fault-tolerant degrees 2 n - 2 and 2 n - 3 are optimal.

Cycles embedding in hypercubes with node failures

The hypercube has been widely used as the interconnection network in parallel computers. The n-dimensional hypercube Q n is a graph having 2 n vertices each labeled with a distinct n-bit binary strings. Two vertices are linked by an edge if and only if their addresses differ exactly in the one bit position. Let f v denote the number of faulty vertices in Q n . For n ⩾ 3 , in this paper, we prove that every fault-free edge and fault-free vertex of Q n lies on a fault-free cycle of every even length from 4 to 2 n − 2 f v inclusive even if f v ⩽ n − 2 . Our results are optimal.

The fat-stack and universal routing in interconnection networks

This paper shows that a novel network called the fat-stack is universally efficient and is suitable for use as an interconnection network in parallel computers. A requirement for the fat-stack to be universal is that link capacities double up the levels of the network. The fat-stack resembles the fat-tree and the fat-pyramid in hardware structure, but it has unique strengths. It is a construct of an atomic subnetwork unit consisting of one ring and one or more upward links to an upper subnetwork. This simple structure entails easy wirability. The network also uses fewer wires. More importantly, it has the capability to scale up to represent a large-scale distributed network. We developed efficient routing algorithms specific to the fat-stack. Our universality proof shows that a fat-stack variant with increased links and of area Θ ( A ) can simulate any competing network of area A with O ( log A ) overhead independently of wire delay. The universality result implies that the augmented fat-stack of a given size is nearly the best routing network of that size. The augmented fat-stack is the minimal universal network for an O ( log A ) overhead in terms of hardware usage. Actual simulations show that the performance of the augmented fat-stack approaches that of the fat-pyramid and is far higher than that of the fat-tree.

Panconnectivity of locally twisted cubes

The locally twisted cube LTQ n which is a newly introduced interconnection network for parallel computing is a variant of the hypercube Q n . Yang et al. [X. Yang, G.M. Megson, D.J. Evans, Locally twisted cubes are 4-pancyclic, Applied Mathematics Letters 17 (2004) 919–925] proved that LTQ n is Hamiltonian connected and contains a cycle of length from 4 to 2 n for n ≥ 3 . In this work, we improve this result by showing that for any two different vertices u and v in LTQ n ( n ≥ 3 ), there exists a u v -path of length l with d ( u , v ) + 2 ≤ l ≤ 2 n − 1 except for a shortest u v -path.

Internally-Disjoint Paths Problem in Bi-Rotator Graphs

A rotator graph was proposed as a topology for interconnection networks of parallel computers, and it is promising because of its small diameter and small degree. However, a rotator graph is a directed graph that sometimes behaves harmfully when it is applied to actual problems. A bi-rotator graph is obtained by making each edge of a rotator graph bi-directional. In a bi-rotator graph, average distance is improved against a rotator graph with the same number of nodes. In this paper, we give an algorithm for the container problem in bi-rotator graphs with its evaluation results. The solution achieves some fault tolerance such as file distribution based information dispersal technique. The algorithm is of polynomial order of n for an n-bi-rotator graph. It is based on recursion and divided into two cases according to the position of the destination node. The time complexity of the algorithm and the maximum length of paths obtained are estimated to be O(n3) and 4n - 5, respectively. Average performance of the algorithm is also evaluated by computer experiments.

APPROXIMATING HYPERCUBES BY INDEX-SHUFFLE GRAPHS VIA DIRECT-PRODUCT EMULATIONS

Index-shuffle graphs are a family of bounded-degree hypercube-like interconnection networks for parallel computers, introduced by [Baumslag and Obrenić (1997): Index-Shuffle Graphs, …], as an efficient substitute for two standard families of hypercube derivatives: butterflies and shuffle-exchange graphs. In the theoretical framework of graph embedding and network emulations, this paper shows that the index-shuffle graph efficiently approximates the direct-product structure of the hypercube, and thereby has a unique potential to approximate efficiently all of its derivatives. One of the consequences of our results is that any member of the following group of standard bounded-degree hypercube derivatives: butterflies, shuffles, tori, meshes of trees, is emulated by the index-shuffle graph with a slowdown in the order of the logarithm of the slowdown of the most efficient emulation achieved by any other member of this group. Emulation algorithms are presented where the emulation host is the n-dimensional index-shuffle graph Ψn, having N=2n nodes. The emulated graph G is a direct product of the form: G=F0×F1×⋯×Fk-1 where k is a power of 2, and each factor Fi is an instance of any of the following three graph families: cycle, complete binary tree, X-tree. Let the size of each factor be |Fi|≤2nf, where k·nf≤n. The index-shuffle graph Ψn, emulates any factor Fi in the product G with slowdown: O( log k) + O( log nf), which is O( log n) = O( log log N). Any collection of 2ℓ copies of the product G, such that: ℓ+k·nf≤n is emulated by the index-shuffle graph Ψn simultaneously, without any additional slowdown. Relaxing the assumption that k is a power of 2 introduces an additional factor of O( lg *N) into the slowdown.