Interconnection Paradigm Research Articles

INTERTEKSTUALITAS HADIS PEREMPUAN SHALAT BERJAMAAH DI MASJID

This paper examines how to understand hadith in a socio-cultural political context. The author takes the example of the hadith, "Women Pray together in Mosques". The method that the author uses, contextual historical analysis by using the interconnection paradigm. This paper includes a type of literature by referring to Abdul Mustaqim's writing, "The Science of Ma'anil Hadith". The difference between this writing and the writing is, the application of the hadith studied. This writing is interesting and important to study, one of the reasons is, in Ramadan women worshipers in mosques more than in other months, of course it is Caused bythe understanding of the hadith above. Thus, the event gave rise to the Novelty of this writing, to reveal the true meaning of the hadith above. Among the conclusions of this paper : (1) The Importance of Asbabul Wurud, Stilistic, Socio-Historical Approach, Contextual-Redaction Analysis, destination, InterconnectionParadigm (Anthropology, Sociology, Psychology) in understanding hadith. (2) In considering the Socio-Cultural Context of Politics in understanding hadith, there is expected to be a compromise and dialogue between the use of hadith in the context of the past and the current context. (3) There is a hadith that seems mukhtalif about the virtues of women's prayers in the mosque. After being analyzed, it shows that: "There are virtues and wisdoms for women who pray in mosques rather than praying at home, especially in this day and age, while still paying attention to various conditions, conditions and ethics".

SPIRITUALITAS DALAM PERSPEKTIF TASAWUF DAN NEUROSAINS: RELASI KOMPLEMENTER ATAU KOMPARTEMEN?

Academic debates about spirituality have been going on for a long time with varied narratives. Sufism, as one who also discussed it, presents a view of spirituality in terms of Islamic metaphysics and meta-psychological understanding in the paradigm of interconnection between creation and the Creator. Meanwhile, Neuroscience, as a new science developed from the findings of Santiago Ramón y Cajal (1852-1934) regarding the nerve function of the human brain, presents a different view and tends to be rational, logical, and materialistic. This paper is a comparative study that discusses how the two sciences describe their explanations of spirituality. This literature research observes a number of relevant references, the latest research results, some debates in several forums, and then dissects it using critical discourse analysis. The results obtained indicate that there is a contradictory explanation on the one hand or a (separate) compartment between the meaning of spirituality in the Sufism perspective and the Neuroscience point of view. On the opposite side, there are several research efforts that elaborate spirituality in Sufism to have a complementary relationship (complementary) with Neuroscience. Even so, there is a kind of narrative impression that forces the concept of spirituality according to Neuroscience to support the conception of spirituality in the view of Sufism. As a follow-up discussion regarding this matter, it can be seen that there is a kind of research tendency that is testimonial and seeks confirmation of the initial assumptions of their research and builds arguments based on their tastes of knowledge.

SPIRITUALITAS DALAM PERSPEKTIF TASAWUF DAN NEUROSAINS: RELASI KOMPLEMENTER ATAU KOMPARTEMEN?

Academic debates about spirituality have been going on for a long time with varied narratives. Sufism, as one who also discussed it, presents a view of spirituality in terms of Islamic metaphysics and meta-psychological understanding in the paradigm of interconnection between creation and the Creator. Meanwhile, Neuroscience, as a new science developed from the findings of Santiago Ramón y Cajal (1852-1934) regarding the nerve function of the human brain, presents a different view and tends to be rational, logical, and materialistic. This paper is a comparative study that discusses how the two sciences describe their explanations of spirituality. This literature research observes a number of relevant references, the latest research results, some debates in several forums, and then dissects it using critical discourse analysis. The results obtained indicate that there is a contradictory explanation on the one hand or a (separate) compartment between the meaning of spirituality in the Sufism perspective and the Neuroscience point of view. On the opposite side, there are several research efforts that elaborate spirituality in Sufism to have a complementary relationship (complementary) with Neuroscience. Even so, there is a kind of narrative impression that forces the concept of spirituality according to Neuroscience to support the conception of spirituality in the view of Sufism. As a follow-up discussion regarding this matter, it can be seen that there is a kind of research tendency that is testimonial and seeks confirmation of the initial assumptions of their research and builds arguments based on their tastes of knowledge.

Integrated Bodies: Language, Art, and Infrastructure in Planetary Health Education

The Planetary Health Education Framework recognizes the interdependence of human health and the health of planetary ecosystems, and centers its guidance on the paradigm of human interconnection within nature. Through the author's scholarship and art, she addresses this "paradigm work" to heal the human-nature divide. This essay explores ideas for the role of language, art, and infrastructure in supporting Planetary Health Education using the example of Earth Systems Journey, which is both an art form and a curriculum model for experiential, art-led environmental education about human integration within nature.

Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA

In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper presents the flexible placement of spare core onto Torus topology-based NoC design by considering core faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology using an FPGA. Experiments have been done by taking different multimedia and synthetic application benchmarks. This has been done in both static and dynamic simulation environments followed by hardware implementation. In the static simulation environment, the experimentations are carried out by scaling the network size and router faults in the network. The results obtained from our approach outperform the methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size, our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of the proposed approach over the approaches presented in the literature.

Training of lawyers in the field of megascience projects: innovations in legal education

The article is devoted to the analysis of the prospects for the development of educational programs aimed at training lawyers in the field of megascience projects. Legal support of megascience projects involves legal support of intellectual resources and protection of the results of intellectual activity, legal regulation of financing of these projects, international legal regulation of scientific and technical cooperation, legal support of cyber security, information-law (including anti-defamation) support of media security of these projects, etc. The authors consider the model of educational training of lawyers for megascience projects in the paradigm of interconnection and interdependence of innovative social relations, science, and education. R&D intensity (knowledge-intensity) of educational training of lawyers in the field of megascience is justified and considered as a feature that is no less significant than practice-orientedness (applied directedness), ensuring not only the short-term competitiveness of educational products, but also their long-term and stable prospects due to the incorporation of the latest cutting-edge R&D achievements into education. The authors suggest a term ‘innovative programs for forward-looking areas’ and analyze their capacity for legal support of megascience projects (the current innovative programs implemented at Kutafin University (MSAL) and the MSAL scientific projects that can be the basis for new educational programs). The authors consider the principles for the implementation of innovative programs for forward-looking areas: fundamentality and practice-orientedness (including the institution of ‘community of practice’ and the mentoring institution), R&D intensity, networking, meta-learning etc.

AMIN ABDULLAH dan PARADIGMA INTEGRASI-INTERKONEKSI

Abstract. The amin abdulllah’s thought is birth by the background of the dichotomous phenomena between religion and science can’t be united and stand donelike there is dividing wall each other. To finish the problem of dichotomical science, Amin Abdullah put out a paradigm of integration-interconnection that is now used by UIN Sunan Kalijaga to the development og the science. A paradigm of integration-interconnection that connect between religion and science. By integrating of scientific triangle, that are: hadlarah an-nash, hadlarah al-ilm, and hadlarah al falsafah. The religion and science have relevant relantionship to education in university. The paradigm of integration interconnection will be solution to dichotomis between religion and science. The method would be used is deepen of library with a journal, article and other. Journal making addressed to know Amin Abdullah’s though and integration-interconnection’s paradigm.Keywords: Amin Abdullah, Integration-Interconnection Paradigm, UIN Sunan Kalijaga.

Evolving optical interconnection topology: from survivable rings to resilient meshes

Physical topologies are evolving from elementary survivable rings into complex mesh networks. Nevertheless, no topology model is known to provide an economic, systematic, and flexible interconnection paradigm for ensuring that those meshes bear resilience features. This paper argues that intrinsic resilience can be brought by twin graph topologies, as they satisfy equal length disjoint path property with minimal number of physical links. Also, they benefit from property preserving recursive methods to graciously scale up/down and merge/split topologies. An exhaustive investigation is performed across twin graph families composing networks from 4 to 17 nodes, whereas diverse real-world topologies and ring networks are used as benchmarks. First, we illustrate the growing and the merging processes, and discuss the topology diversity of twin graphs. We analyze the impact of single cable cuts between neighbouring nodes, then we stress topologies with 2, 3, and 4 simultaneous cable cuts. Improved resiliency is seen for neighbor nodes and also reduction of cut sets able to disconnect the twin topologies in comparison with real-world networks. At transport layer, we derive and validate an upper bound for additional capacity required to implement $$1+1$$ path dedicated protection. As networks grow larger, this protection cost is consistently reduced compared to benchmark topologies. We also test the suitability of our approach at optical layer regarding transponders consumption. Finally, we present as a use case the redesign of CESNET into a resilient network.

Co-Fabrication of Microcoaxial Interconnects and Substrate Junctions for Multichip Microelectronic Systems

RF and millimeter-wave designers continue to use wire bonds and flip chip in their designs when bonding chips or multichip systems. Due to electrical and mechanical constraints of wire bonding and flip chip, designers are forced to compensate for mismatched impedances, high loss, or mechanically unreliable interconnects. In this article, we propose microcoaxial cables (MCCs) as an alternative interconnect, specifically, 30–75- $\Omega $ MCCs for signals, and low-inductance MCCs for bias and supply. In addition, each shielded interconnect provides sufficient isolation to prevent electromagnetic interference (EMI) and crosstalk. The in situ fabrication method presented here utilizes only conventional wire bonding and microfabrication techniques, providing a high-feasibility path toward a new interconnect paradigm based on MCCs. Each cable measured consists of a 25.4- $\mu \text{m}$ gold bond wire coated first with a dielectric and then with a 5.0- $\mu \text{m}$ -thick gold shield. MCCs appropriate for signals have a 38- $\mu \text{m}$ -thick Parylene C dielectric and a characteristic impedance of 39– $68~\Omega $ . For the first time, to the best of our knowledge, we introduce low-inductance MCCs, where the dielectrics evaluated are 1.0- $\mu \text{m}$ -thick Parylene C dielectric and 100-nm-thick HfO2. Their inductances are measured to be no more than 140 pH/mm. For 3.5-mm-long wire with a 0.51-mm pitch, the crosstalk is −62 dB at 1 GHz for signal MCCs. Crosstalk increases to −30 dB at 26.5 GHz.

An automated fault-tolerant route discovery with congestion control using TFRF model for 3D network-on-chips

As one of the principle patterns of communication technology for 3D-integrated circuit (ICs), the 3D-networks-on-chips (3D-NoCs) have lot of attention from scientific research community. 3D-NoCs has been provided as a propitious solution merging the high parallelism of network-on-chip (NoCs) interconnect paradigm with the high-performance and lower interconnect-power of three-dimensional integration circuits. For the permanent link faults, the fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of the 2D NoCs. In this paper, we propose a triggered fault-free route forwarding model called TFRF for 3D mesh NoCs without requiring any virtual channels (VCs).TFRF is a deadlock-free scheme by adopting a logic-based routing named TFRF guided by a turn activating rule model. The experimental results show that TFRF possesses better performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing schemes.

A Comparative Study on Automated Fault—Tolerant Route Discovery with Congestion Control Using TFRF Model for 3-D Network-on-Chips

In recent times, with the capaciousness of on-chip cores endorsed over rapid technology scaling, network-on-chips (NoCs) are turning out to be a crucial element of entire system power performance characteristics. 3D-NoCs has been contributed as an auspicious solution merging the high parallelism of NoCs interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional Integrated Circuits (ICs). For the permanent link faults, an impressive mechanism contemplated is the fault-tolerant routing scheme to provide the performance of the 2-D NoCs. In this article, our proposed Triggered Fault-Free Route Forwarding model (TFRF) for 3-D Mesh NoCs without desiring any virtual channels (VCs) is compared with existing approaches with the intention of validating the performance. The experimental results of our proposed TFRF is evaluated and the performance is enhanced in terms of reliability with minimized overhead and the analytical phase details of the evaluation outcomes.

Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation

ABSTRACTAs the technology is scaling down more number of processing elements are integrated on to a single chip, namely system-on-chips (SoCs). Using traditional bus architecture in SoCs, communication among different processing elements is difficult. Hence, to overcome it, a new on-chip interconnection paradigm known as network-on-chip (NoC) has been proposed. The communication among different processing elements in NoCs is achieved using packet switching technique. In nano-scale era, NoCs are prone to vulnerable faults and designing an NoC to meet current application requirements is highly challenging. Hence, there is a need to develop reliable and efficient Fault-tolerant NoC designs. This paper presents a novel Fault-Tolerant NoC design for butterfly-fat-tree (BFT) topology with flexible spare core placement by taking different benchmark applications into consideration. The major challenge in fault-tolerant NoC is placement of spare core in the event of core failure in BFT network. Therefore, we have proposed an integer linear programming (ILP)-based exact method and particle swarm optimisation (PSO)-based meta-heuristic technique to place the spare core in a BFT network. Our major contribution is to place the spare core in BFT network such that system performance is improved in terms of communication cost, network latency, and router power consumption. Experimentations have been performed on several application benchmarks reported in the literature, (i) by varying the network size with fixed fault-percentage in the network, (ii) by varying the percentage of faults while fixing the network size and (iii) by taking multiple failed cores as a user input. We have compared overall communication cost obtained using our approaches with native fault-free approach. We have also compared overall communication cost and CPU runtime between ILP and PSO. The results show improvement in terms of overall communication cost, average network latency and network power consumption using our approaches compared to fault-free approach in BFT networks.

Seismic upgrade of structures using the H∞ control problem for a general system interconnection paradigm

This paper presents a novel approach for the modification and seismic upgrading of shear-frame structures by attaining and implementing optimal changes in stiffness, changes in mass, and added damping (referred to as the structural changes). A general system interconnection paradigm is proposed and presented. The paradigm is assigned with a passive controller that consists of the structural changes and has simulated feedback on the structural response and the seismic excitation. A newly formulated optimization problem is required to satisfy constraints on maximum total story accelerations and maximum interstory drifts. The objective is to minimize the H∞ norm of a singled out response of the general system interconnection closed-loop transfer function matrix, making it a single-input single-output transfer function case. The control problem is solved by utilizing the first-order steepest descent method, an H∞ synthesis algorithm, for calculating the free parameters of a passive controller which consists of the structural changes. Their method is further enhanced for seismic design needs, by imposing boundaries on the free parameters according to the dynamic response of the structure to given ground motion ensemble. Two numerical examples of a 9-story shear-frame structure and 10-story moment resisting frame are studied. Optimal changes in mass, stiffness, and damping are obtained, and results show significant improvement in the peak dynamic response. The results indicate the efficiency of the proposed procedure that possesses the capability of attaining optimal changes in all physical characteristics of the structure (mass, stiffness, and damping) while adhering to preassigned maximum response levels.

Fragmentation as an agent of integration: Subnational authorities in EU law

This article draws on the theory of “federalism as the new nationalism” to illustrate that regulatory fragmentation is not necessarily synonymous with disintegration. Regulatory fragmentation can rather be conceptualized as a tool assisting European integration. Looking at the status of subnational authorities (SNAs) in EU law, the article identifies decisions of the Court of Justice of the European Union (CJEU) in free movement law that illustrate that SNAs can be conceived as valuable insiders, rather than threatening outsiders, of European law. This account, which indicates that SNAs’ contribution to European legal integration is in many ways analogous to that of the Member States, stands in contrast with the European Treaties that recognize only two levels of public authority as SNAs are seen as a predominantly domestic phenomenon of little relevance for the supranational project. My analysis underscores that SNAs and their norms do not exist in a sphere separate from that of EU law. It highlights diverse interactions between the subnational and the supranational and suggests that the influence of levels of public authority can best be captured by a paradigm of interconnection rather than separation. Indeed, contrary to commonplace assumptions, it is not actors’ formal status, anchored in notions such as independence, sovereignty, and autonomous competences but the manifold functional interactions between them that shape the polycentric Union. Through this functional lens we confirm what federalism scholars have observed in the USA, namely, that “decentralization can serve rather than undermine the project of integration.”

Topology exploration of a thermally resilient wavelength-based ONoC

With the growing number of cores, high-performance systems face power challenges due to dominating communication power. Thus, attaining energy efficient high-bandwidth inter-core communication nominates photonic network-on chip as the most promising interconnection paradigm. Although photonic networks pave the way for extremely higher performance communications, their intrinsic susceptibility to thermal fluctuations intimidates reliability of system. This necessitates the development of methodologies to analyze and model thermal effects on network behavior. In this paper, we model temperature fluctuations of optical chips and analyze photonic networks in a holistic approach. We present a novel wavelength-routed all-optical mesh network-on-chip, which significantly reduces optical contention scenarios throughout the network. While leveraging slightly larger number of wavelengths, it attains tolerance against thermal-induced faults. Our proposed architecture is compared against a popular wavelength-routed network, i.e. λ-router, in terms of throughput, in the presence of temperature drifts. Moreover, reliability comparison addressing fault rate in terms of temperature variation reveals that our proposed architecture significantly outperforms λ-router, as its competitor.

Lighting Up On-Chip Communications with Photonics: Design Tradeoffs for Optical NoC Architectures

Photonic on-chip interconnects are today considered a major pathway to face the insatiable performance demand of manycore computers within tight power constraints. This article provides a broad overview of the opportunities and challenges posed at the architecture level by this new interconnect paradigm. In fact, silicon Photonics introduces many new design tradeoffs, having no electronic equivalent, involving aspects such as wavelength selectivity, physical constraints, and spectral parallelism. As highlighted throughout the paper, getting a cross-cutting understanding of these tradeoffs is essential for harnessing the full potential of on-chip Photonics.

Through Global Sharing to Improve Network Efficiency for Radio-Frequency Interconnect Based Network-on-Chip

According to the International Technology Roadmap for Semiconductors, improving characteristics of metal wires will no longer satisfy performance requirements, and new interconnect paradigms are needed. Radio frequency interconnect (RF-I) enjoys better CMOS compatibility compared with other alternatives, and is exploited as express shortcuts overlaid traditional network-on-chip (NoC) topologies. However, the efficient utilization of on-chip communication bandwidth provided by RF interconnects still remains an open problem. To make effective use of scarce on-chip RF-I for different traffic patterns, system model of NoC with shared RF-I (SRFNoC) is constructed first time in this paper, along with detailed design methodology. A light-weighted arbitration mechanism is utilized for sharing resource allocation, and a new mapping algorithm communication weight and simulated annealing is proposed for topology distribution. Both static and dynamic routings for SRFNoC are also discussed in detail. The results of experiment showed that, compared with the NoC with long-range wired links and representative network-on-chip with exclusive allocated radio frequency interconnect, the proposed network can get better communication efficiency with less resource overhead.

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multi-core revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies. This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS ( globally asynchronous locally synchronous ) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.

Contention-Aware Energy Management Scheme for NoC-Based Multicore Real-Time Systems

Network-on-Chip (NoC) has emerged as interconnect paradigm in state-of-the-art multi/many core architectures. Voltage and frequency island (VFI) was recently adopted as an effective energy management technique for large scale multicore chip designs. Focusing on NoCand VFI-based multi/many core real-time systems with Dynamic Voltage and Frequency Scaling (DVFS) capability, we study both static and dynamic contention-aware energy management schemes for task set with precedence relationships and a common deadline. First, our static schemes utilize two approaches with contention awareness to obtain the mapping of tasks to cores together with scheduling of communications on NoC for minimizing makespan, and thus can potentially lower uniform scaled frequency for cores and links while meeting the timeliness. Next, different from other existing schemes, by incorporating the latency due to network congestions into the analysis, our dynamic contention-aware energy management schemes perform the allocation of feasible slack to tasks and communications simultaneously for further energy savings, subject to common voltage and frequency limitations of VFI and timing constraints of task set. The results through extensive simulations and case studies show that, compared to heuristicbased and INLP-based task mapping solutions (with pessimistic estimation of communication contention), our static scheme can obtain better energy savings (e.g., 25 percent more). The results also show that our dynamic scheme can save up to 45 percent more energy compared to our static scheme under deadline guarantee, while the online scheme ignoring the traffic congestions in NoC can result in serious deadline violation and usually more energy consumption (e.g., 15 percent more).

Morphing Bus: A New Paradigm in Peripheral Interconnect Bus

Modern digital peripheral interconnect buses are typically described as one of the two types, serial or parallel, based on whether or not the physical data channel(s) is (are) shared across the bits of a coherent data word. Conventional serial and parallel buses operate in a time-multiplexed mode, allowing access to only one peripheral device at a time. PCIexpress expanded this simple bifurcation by combining serial data channels with simultaneous access to multiple peripheral devices (or multiple regions of the same peripheral). Moving to that nontime-multiplexed mode opened a new dimension by which bus architectures could be classified. Under this taxonomy of serial versus parallel and time-multiplexed versus nontime multiplexed, our Morphing Bus presents a new paradigm that fills the parallel, nontime multiplexed interconnect niche. Furthermore, the Morphing Bus eliminates the notion of an intermediate data format and thereby obviates the need for bus interface circuitry. Instead of a common data format to which all the sensors and actuators are translated, the Morphing Bus transforms-or morphs-its signal lines to meet the needs of the connected sensors or actuators. For digital sensors and actuators, this morphing is achieved through a field-programmable gate array on the processor side of the bus. As programmable devices begin to incorporate analog signal paths, the Morphing Bus paves the way for integrating analog and digital signals into a single bus paradigm. The efficacy of the Morphing Bus is verified via implementation on a miniature robot and the bandwidth of the bus implementation is experimentally characterized. Its unique physical I/O stack in the form of a helical structure provides efficient cooling and power distribution for compact embedded systems in addition to the novel interconnect paradigm.