Interconnection Paradigm Research Articles

Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures

Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause corrupted message transfer or even catastrophic system failures. Therefore, a 3D-NoC system should be fault-tolerant to transient malfunctions or permanent physical damages.In this paper, we present an efficient fault-tolerant routing algorithm, called Hybrid-Look-Ahead-Fault-Tolerant (HLAFT), which takes advantage of both local and look-ahead routing to boost the performance of 3D-NoC systems while ensuring fault-tolerance. A deadlock-recovery technique associated with HLAFT, named Random-Access-Buffer (RAB), is also presented. RAB takes advantage of look-ahead routing to detect and remove deadlock with no considerably additional hardware complexity. We implemented the proposed algorithm and deadlock-recovery technique on a real 3D-NoC architecture (3D-OASIS-NoC11This project is partially supported by Competitive research funding, Ref. P1-5, Fukushima, Japan.) and prototyped it on FPGA. Evaluation results show that the proposed algorithm performs better than XYZ, even when considering high fault-rates (i.e., ≥ 20%), and outperforms our previously designed Look-Ahead-Fault-Tolerant routing (LAFT) demonstrated in latency/flit reduction that can reach 12.5% and a throughput enhancement reaching 11.8% in addition to 7.2% dynamic-power saving thanks to the Power-management module integrated with HLAFT.

Dual partitioning multicasting for high-performance on-chip networks

As the number of cores integrated onto a single chip increases, power dissipation and network latency become ever-increasingly stringent. On-chip network provides an efficient and scalable interconnection paradigm for chip multiprocessors (CMPs), wherein one-to-many (multicast) communication is universal for such platforms. Without efficient multicasting support, traditional unicasting on-chip networks will be low efficiency in tackling such multicast communication. In this paper, we propose Dual Partitioning Multicasting (DPM) to reduce packet latency and balance network resource utilization. Specifically, DPM scheme adaptively makes routing decisions based on the network load-balance level as well as the link sharing patterns characterized by the distribution of the multicasting destinations. Extensive experimental results for synthetic traffic as well as real applications show that compared with the recently proposed RPM scheme, DPM significantly reduces the average packet latency and mitigates the network power consumption. More importantly, DPM is highly scalable for future on-chip networks with heavy traffic load and varieties of traffic patterns.

Regional cache organization for NoC based many-core processors

As the number of Processing Elements (PEs) on a single chip keeps growing, we are now facing with slower memory references due to longer wire delay, intenser on-chip resource contention and higher network traffic congestion. Network on Chip (NoC) is now considered as a promising paradigm of inter-core connection for future many-core processors. In this paper, we examined how the regional cache organizations drastically reduce the average network latency, and proposed a regional cache architecture with Delegate Memory Management Units (D-MMUs) for NoC based processors. Experiments showed that the L2 cache access latency is largely determined by its organization and inter-connection paradigm with PEs in the NoC, and that the regional organization is essentially important for better NoC cache performance.

Modified bundled-data as a new protocol for NoC asynchronous links

Asynchronous interconnection paradigm in NoCs has attracted many system designers in the recent years, through its different possible implementation strategies. In this paper, we present a new insight on how to categorize asynchronous protocols and explore a suitable protocol for the NoC asynchronous links. The new categorization criterion is based on the type of dependency between data transferring and handshaking tasks in a protocol. Furthermore, a new protocol called modified bundled-data (MBD) is introduced. MBD is a bundled-data-like protocol with two pairs of two-phase dual-rail encoded parity lines on the lateral sides of data lines, besides one two-phase acknowledgement line. The new protocol is evaluated by comparing its simulation results with those of bundled-data (BD) and dual-rail (DR) protocols on a 32-bit flit NoC asynchronous link. For this purpose, a new comprehensive interconnect model has been developed. The simulation results show that the new protocol's features such as power consumption, throughput, and latency are comparable with BD protocol's, while its signal integrity features are close to DR's.

Cost models for QoS-differentiated interconnecting and wholesale access services in future generation networks

Currently, network operators and Internet service providers are offering "Triple Play" products integrating services with different Quality of Service (QoS) requirements. It is leading to Internet traffic with strong service integration under an all-IP-based broadband network platform. However, new multimedia service offers require individual QoS guarantees for each type of services. The interconnection between different providers necessitates the reconsideration of the actual cost schemes. Interconnection and wholesale access services (It is an extension of "wholesale network" definition, where Telco's physical network and equipment are "shared" to many independent Service Providers. If the incumbent offers broadband access services, the rest of the alternative providers have recourse to the incumbent's "wholesale access service". Bitstream service is the most important service of this type, actually regulated over DSL and cable networks.) appear to be a simple solution, but the consideration of QoS parameters requires an extension of the current network dimensioning methods based mainly on the average bandwidth demand from each user. This paper proposes a cost model which considers QoS parameters and, based on the "Total Element based Long Run Incremental Cost" (TELRIC) model, is applied to the wholesale access and interconnection paradigm. Three traffic engineering methods are considered and studied for network dimensioning. Hereby the aim is to guarantee the QoS of the different services: complete traffic segregation under virtual tunnels, complete traffic integration by over-engineering and partial traffic integration using a priority queuing scheme. The proposed method enables the development of a specific cost scheme based on a complete scenario considering different types of users. The variety of used IP applications suppose direct implications over different levels of interconnection, mainly at the low-level Metro access and the high-level edge node.

Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies

This special issue highlights recent investigations of various revolutionary interconnect paradigms as to whether they can deliver on the promise of greater integration, high performance, good scalability, and high energy efficiency in future SoCs and other computing platforms. The selected articles represent a wide range of emerging interconnects, from carbon nanotubes, to optical, RF, and on-chip wireless communications.

Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation

The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology for integrating a very high number of intellectual property (IP) blocks in a single die. The achievable performance benefit arising out of adopting NoCs is constrained by the performance limitation imposed by the metal wire, which is the physical realization of communication channels. With technology scaling, only depending on the material innovation will extend the lifetime of conventional interconnect systems a few technology generations. According to International Technology Roadmap for Semiconductors (ITRS) for the longer term, new interconnect paradigms are in need. The conventional two dimensional (2D) integrated circuit (IC) has limited floor-planning choices, and consequently it limits the performance enhancements arising out of NoC architectures. Three dimensional (3D) ICs are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, NoC is an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. In this paper we evaluate the performance of 3D NoC architectures and demonstrate their superior functionality in terms of throughput, latency, energy dissipation and wiring area overhead compared to traditional 2D implementations.

A Cross-Layer Architecture of Wireless Sensor Networks for Target Tracking

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We propose the Low Energy Self-Organizing Protocol (LESOP) for target tracking in dense wireless sensor networks. A cross-layer design perspective is adopted in LESOP for high protocol efficiency, where direct interactions between the Application layer and the Medium Access Control (MAC) layer are exploited. Unlike the classical Open Systems Interconnect (OSI) paradigm of communication networks, the Transport and Network layers are excluded in LESOP to simplify the protocol stack. A lightweight yet efficient target localization algorithm is proposed and implemented, and a Quality of Service (QoS) knob is found to control the tradeoff between the tracking error and the network energy consumption. Furthermore, LESOP serves as the first example in demonstrating the migration from the OSI paradigm to the Embedded Wireless Interconnect (EWI) architecture platform, a two-layer efficient architecture proposed here for wireless sensor networks. </para>

Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research

The network-on-chip paradigm is an emerging paradigm that effectively addresses and presumably can overcome the many on-chip interconnection and communication challenges that already exist in today's chips or will likely occur in future chips. Effective on-chip implementation of network-based interconnect paradigms requires developing and deploying a whole new set of infrastructure IPs and supporting tools and methodologies. This special issue illustrates how, to date, engineers have successfully deployed NoCs to meet certain very-aggressive specifications. At the same time, the articles reveal many issues and challenges that require solutions if the NoC paradigm will indeed become a panacea or quasi-panacea for tomorrow’s SoCs.

Health for All by the Year 2000—Cultural Handicaps and Possible Solutions

Health conditions, as part-and-parcel of man's project of life, reflect the way people choose to live together as a collective body. Health behavior analysis cannot ignore cultural conditions that foster different ways of life. Health practices are not a matter of mere compliance to a set of norms, but a cultural product. Professional competencies ask for a sufficient curriculum, a full proficiency. Myth and logos should be related and the symbolic form everyday experience assumes should be discussed. Paradigmatic thought should give place to mutual growth and subjective and objective aspects of reality should have an equal and complementary standing. Disciplinarity and multidisciplinarity should evolve into interdisciplinarity, as a paradigm of cooperation, interconnection, equality, and flexibility in order to define curricula and programs. Conceptual ecology of science should be emphasized. New concepts of growth, wealth, work, and power should be discussed as a way of attaining health for all in the year 2000.