Interprocessor Communication Research Articles

Research and Analysis Process of Android Communication Platform in AIDL Model

AIDL is a android platform to describe the inter process communication interface description language, can simplify the process of data exchange between the format and data code.Research on AIDL communication mechanism has an important significance to the realization of the Android platform interprocess communication. This paper analyzed the AIDL model and the communication mechanism and gives examples to discuss.

Subsonic flow boundary conditions for the direct simulation Monte Carlo method

The performance of different types of boundary conditions used in direct simulation Monte Carlo models of subsonic flows for single species flow fields is assessed in this study. An inlet boundary condition that permits the specification of pressure and temperature is investigated, as well as one that permits the specification of mass flow rate and temperature. A new inlet boundary condition is suggested that permits the total mass flow rate to be specified without requiring inter-processor communication during a parallel computation. Two types of outlet boundary conditions are investigated, one in which the outlet pressure is maintained by controlling the porosity of the outlet surface, and another in which particles are introduced at the outlet with properties such that the desired pressure is maintained. Each of the boundary conditions investigated produce flow field results for a single species, microchannel flow that are in good agreement with an analytical solution of the flow field and previously reported results. However, a simulation of a more complicated multi-species flow inside a vapor deposition reactor shows that some of the predicted flow field and surface properties are a function of the type of outlet boundary condition used.

A New Approach for Inter Process Communication with Hybrid of Message Passing Mechanism and Event based Software Architecture

In this paper, we use software architecture style based on event-driven and message passing communication method and determine a framework for interaction among practicable processes on Operating System (OS). In the proposed method, the required data are sent to the process or other processes in a standard message frame and with determined structure to the OS, then, the OS distributes the received message considering its recipient processes in the system, rather a process communicates directly with other specific process. The major features of the proposed method include the synchronization among the processes, the simplicity of implementation, easy extensibility, remote access which finally can improve the interaction between the OS and processes. Along with producing the systems based on an integrated frame, we obtain a determined standard in Inter Process Communication (IPC) by mediating an OS. Keywords: Event-driven, IPC, Message Passing, OS, Software Architecture

Web services-based text-mining demonstrates broad impacts for interoperability and process simplification.

The Critical Assessment of Information Extraction systems in Biology (BioCreAtIvE) challenge evaluation tasks collectively represent a community-wide effort to evaluate a variety of text-mining and information extraction systems applied to the biological domain. The BioCreative IV Workshop included five independent subject areas, including Track 3, which focused on named-entity recognition (NER) for the Comparative Toxicogenomics Database (CTD; http://ctdbase.org). Previously, CTD had organized document ranking and NER-related tasks for the BioCreative Workshop 2012; a key finding of that effort was that interoperability and integration complexity were major impediments to the direct application of the systems to CTD's text-mining pipeline. This underscored a prevailing problem with software integration efforts. Major interoperability-related issues included lack of process modularity, operating system incompatibility, tool configuration complexity and lack of standardization of high-level inter-process communications. One approach to potentially mitigate interoperability and general integration issues is the use of Web services to abstract implementation details; rather than integrating NER tools directly, HTTP-based calls from CTD's asynchronous, batch-oriented text-mining pipeline could be made to remote NER Web services for recognition of specific biological terms using BioC (an emerging family of XML formats) for inter-process communications. To test this concept, participating groups developed Representational State Transfer /BioC-compliant Web services tailored to CTD's NER requirements. Participants were provided with a comprehensive set of training materials. CTD evaluated results obtained from the remote Web service-based URLs against a test data set of 510 manually curated scientific articles. Twelve groups participated in the challenge. Recall, precision, balanced F-scores and response times were calculated. Top balanced F-scores for gene, chemical and disease NER were 61, 74 and 51%, respectively. Response times ranged from fractions-of-a-second to over a minute per article. We present a description of the challenge and summary of results, demonstrating how curation groups can effectively use interoperable NER technologies to simplify text-mining pipeline implementation.Database URL: http://ctdbase.org/

The Software Architecture for Efficient Distributed Interprocess Communication in Mobile Distributed Systems

The mobile distributed computing applications execute in heterogeneous and dynamic network environments and require efficient as well as reliable interprocess communication (IPC) mechanism. In general, the kernel-level IPC mechanisms offer improved performance as compared to middleware-based systems. This paper proposes the design and implementation of composite software architecture within monolithic kernel to realize high-performance and reliable mobile distributed IPC mechanism supporting mobile computing applications in heterogeneous and dynamic network environments. The performance of software architecture is measured in geographically distributed computing systems executing mobile computing applications. The experimental results illustrate that the proposed software architecture offers significantly improved performance in Ethernet (629 μs/25 Byte ~ 2929 μs/5 KB) as well as in wireless networks (34528 μs/25 Byte ~ 42511 μs/5 KB). The architecture successfully reduces distributed IPC latency in Ethernet (0.899 μs/Byte) and in wireless networks (92.628 μs/Byte). The comparative analysis illustrates that the composite architecture achieves performance enhancements in the range of 12.73 % to 75.84 % as compared to middleware-based IPC mechanisms. The proposed composite software architecture does not require any specific network topology and any specialized communication hardware.

Parallelization of nonuniform loops in supercomputers with distributed memory

A template algorithm for parallel execution of independent iterations of the repetitive loop on a multiprocessor computer with distributed memory is constructed. Regardless of the number of processors, the algorithm must provide efficient utilization of computing capacity under essentially different complexities of iterations and/or performance of processors. The interprocessor data communication and control of par� allel computations are assumed to be implemented using a standard messagepassing interface (MPI), which is widely used in such systems. Existing methods for the loop parallelization are analyzed and the correspond� ing efficiencies are empirically estimated for various models of iteration nonuniformity.

The TH Express high performance interconnect networks

Interconnection network plays an important role in scalable high performance computer (HPC) systems. The TH Express-2 interconnect has been used in MilkyWay-2 system to provide high-bandwidth and low-latency interprocessor communications, and continuous efforts are devoted to the development of our proprietary interconnect. This paper describes the state-of-the-art of our proprietary interconnect, especially emphasizing on the design of network interface. Several key features are introduced, such as user-level communication, remote direct memory access, offload collective operation, and hardware reliable end-to-end communication, etc. The design of a low level message passing infrastructures and an upper message passing services are also proposed. The preliminary performance results demonstrate the efficiency of the TH interconnect interface.

Real-time million-synapse simulation of rat barrel cortex.

Simulations of neural circuits are bounded in scale and speed by available computing resources, and particularly by the differences in parallelism and communication patterns between the brain and high-performance computers. SpiNNaker is a computer architecture designed to address this problem by emulating the structure and function of neural tissue, using very many low-power processors and an interprocessor communication mechanism inspired by axonal arbors. Here we demonstrate that thousand-processor SpiNNaker prototypes can simulate models of the rodent barrel system comprising 50,000 neurons and 50 million synapses. We use the PyNN library to specify models, and the intrinsic features of Python to control experimental procedures and analysis. The models reproduce known thalamocortical response transformations, exhibit known, balanced dynamics of excitation and inhibition, and show a spatiotemporal spread of activity though the superficial cortical layers. These demonstrations are a significant step toward tractable simulations of entire cortical areas on the million-processor SpiNNaker machines in development.

Modular Software Model Checking for Distributed Systems

Distributed systems are complex, being usually composed of several subsystems running in parallel. Concurrent execution and inter-process communication in these systems are prone to errors that are difficult to detect by traditional testing, which does not cover every possible program execution. Unlike testing, model checking can detect such faults in a concurrent system by exploring every possible state of the system. However, most model-checking techniques require that a system be described in a modeling language. Although this simplifies verification, faults may be introduced in the implementation. Recently, some model checkers verify program code at runtime but tend to be limited to stand-alone programs. This paper proposes cache-based model checking, which relaxes this limitation to some extent by verifying one process at a time and running other processes in another execution environment. This approach has been implemented as an extension of Java PathFinder, a Java model checker. It is a scalable and promising technique to handle distributed systems. To support a larger class of distributed systems, a checkpointing tool is also integrated into the verification system. Experimental results on various distributed systems show the capability and scalability of cache-based model checking.

Quatrain: Accelerating Data Aggregation between Multiple Layers

Composition of multiple layers (or components/services) has been a dominant practice in building distributed systems, meanwhile aggregation has become a typical pattern of data flows nowadays. However, the efficiency of data aggregation is usually impaired by multiple layers due to amplified delay. Current solutions based on data/execution flow optimization mostly counteract flexibility, reusability, and isolation of layers abstraction. Otherwise, programmers have to do much error-prone manual programming to optimize communication, and it is complicated in a multithreaded environment. To resolve the dilemma, we propose a new style of inter-process communication that not only optimizes data aggregation but also retains the advantages of layered (or component-based/service-oriented) architecture. Our approach relaxes the traditional definition of procedure and allows a procedure to return multiple times. Specifically, we implement an extended remote procedure calling framework Quatrain to support the new multireturn paradigm. In this paper, we establish the importance of multiple returns, introduce our very simple semantics, and present a new synchronization protocol that frees programmers from multireturn-related thread coordination. Several practical applications are constructed with Quatrain, and the evaluation shows an average of 56% reduction of response time, compared with the traditional calling paradigm, in realistic environments.

Shuttle: Facilitating Inter-Application Interactions for OS-Level Virtualization

OS-level virtualization generates a minimal start-up and run-time overhead on the host OS and thus suits applications that require both good isolation and high efficiency. However, multiple-member applications required for forming a system may need to occasionally communicate across this isolation barrier to cooperate with each other while they are separated in different VMs to isolate intrusion or fault. Such application scenarios are often critical to enterprise-class servers, HPC clusters and intrusion/fault-tolerant systems, etc. We make the first effort to support the inter-application interactions in an OS-level virtualization system without causing a significant compromise on VM isolation. We identify all interactive operations that impact inter-application interactions, including inter-process communications, application invocations, resource name transfers, and application dependencies. We propose Shuttle, a novel approach for facilitating inter-application interactions within and across OS-level virtual machines. Our results demonstrate that Shuttle can correctly address all necessary inter-application interactions while providing good isolation capability for all sample applications on different versions of Windows OS.

Parallel implementation of isothermal and isoenergetic Dissipative Particle Dynamics using Shardlow-like splitting algorithms

A parallel implementation of the Shardlow splitting algorithm (SSA) for Dissipative Particle Dynamics (DPD) simulations is presented. The isothermal and isoenergetic SSA implementations are compared to the DPD version of the velocity-Verlet integrator in terms of numerical stability and performance. The integrator stability is assessed by monitoring temperature, pressure and total energy for both the standard and ideal DPD fluid models. The SSA requires special consideration due to its recursive nature resulting in more inter-processor communication as compared to traditional DPD integrators. Nevertheless, this work demonstrates that the SSA exhibits stability over longer time steps that justify its regular use in parallel, multi-core applications. For the computer architecture used in this study, a factor of 10–100 speedup is achieved in the overall time-to-solution for isoenergetic DPD simulations and a 15–34 speedup is achieved for the isothermal DPD simulations.

CDMA Technique with Inter-process Communication

A novel implementation of Inter process communication in CDMA NOC is proposed. In this study, the orthogonality properties of a Walsh code are used to route data packets between the IP-Cores.The asynchronous circuit design with combinational logic (Gate level design) is used for transmission and receiving circuits, along with ip-cores and reduces the processing time and resource utilization. The use of asynchronous pipelined core design process increases the operating frequency as well. The data transfers over IP-Core based interconnect is implemented on gate level. The latency and throughput values are obtained for variable payload size. The performance of asynchronous and synchronous communication are measured and analyzed.

ASDEX Upgrade Discharge Control System—A real-time plasma control framework

ASDEX Upgrade is a fusion experiment with a size and complexity to allow extrapolation of technical and physical conditions and requirements to devices like ITER and even beyond. In addressing advanced physics topics it makes extensive use of sophisticated real-time control methods. It comprises real-time diagnostic integration, dynamically adaptable multivariable feedback schemes, actuator management including load distribution schemes and a powerful monitoring and pulse supervision concept based on segment scheduling and exception handling. The Discharge Control System (DCS) supplies all this functionality on base of a modular software framework architecture designed for real-time operation. It provides system-wide services like workflow management, logging and archiving, self-monitoring and inter-process communication on Linux, VxWorks and Solaris operating systems. By default DCS supports distributed computing, and a communication layer allows multi-directional signal transfer and data-driven process synchronisation over shared memory as well as over a number of real-time networks. The entire system is built following the same common design concept combining a rich set of re-usable generic but highly customisable components with a configuration-driven component deployment method.We will give an overview on the architectural concepts as well as on the outstanding capabilities of DCS in the domains of inter-process communication, generic feedback control and pulse supervision. In each of these domains, DCS has contributed important ideas and methods to the on-going design of the ITER plasma control system. We will identify and describe these essential features and illustrate them with examples from ASDEX Upgrade operation.

Extending JPF to verify distributed systems

This paper presents our work on model checking distributed applications. We refer to distributed applications as a collection of communicating processes, regardless of their physical locations and the communication means. Our work targets applications written in Java. It relies on the multiprocess support included in Java Pathfinder (JPF) version 7 which allow for verifying the bytecode of distributed applications. The basic support for distributed applications in JPF does not account for communication between processes. In this work, we address this limitation. The work is implemented as a JPF extension which models inter- process communication (IPC) mechanisms. It uses a form of partial order reduction (POR) to explore all possible executions of a distributed Java application. Moreover, our approach provides a functionality to check the given distributed application against possible network failures which can occur at the operating system or the hardware layer.

Electronic Data Interchange on Logistics System Based on Embedded Linux

EDI is an important part of logistics information technology and is also the basis and prerequisite of the implementation for supply chain logistics information system. This paper researches on electronic data interexchange of embedded Linux to promote EDI technology to be widely used in the field of logistics control. First, the paper studies kernel structure of embedded Linux that includes process scheduling, memory management, virtual file system, network interface, inter-process communication and methods and procedures of kernel cutting; then, we can research a number of issues in the logistics field of electronic data interchange supported by embedded Linux. The issues include workflow, hierarchical structure and main applications and so on. Contents of this paper extend the application area and support environment of EDI. In addition, it is an important research direction in logistics informatization used EDI technology.

Software-Enabled Investigation in Metaheuristic Power Grid Optimization

Actual developments in power grid research, analysis, and operation are dominated clearly by the strong convergence of electrical engineering with information technology. Hence, new control abilities in power grids come up that revolutionize traditional optimization issues, requiring novel solution methods. At the same time, heuristic algorithms have emerged to be highly capable of handling those new optimization problems. In this work, a simulation-based optimization approach is proposed that enables investigation with metaheuristic algorithms for domain experts, where especially the power engineering point of view gets highlighted. HeuristicLab is demonstrated as a framework for optimization, which facilitates usage and development of optimization algorithms in a way that is attractive not only to computer scientists. From a software point of view, architectural aspects are treated that enable the decoupling of optimization algorithms and problems, which is a basic fundament of the framework. Further, interprocess communication is discussed that enables the interaction of optimization algorithms and simulation problems, and a practical showcase demonstrates the framework's application to real-world power grid optimization issues.

Real-Time and Real-Fast Performance of General-Purpose and Real-Time Operating Systems in Multithreaded Physical Simulation of Complex Mechanical Systems

Physical simulation is a valuable tool in many fields of engineering for the tasks of design, prototyping, and testing. General-purpose operating systems (GPOS) are designed for real-fast tasks, such as offline simulation of complex physical models that should finish as soon as possible. Interfacing hardware at a given rate (as in a hardware-in-the-loop test) requires instead maximizing time determinism, for which real-time operating systems (RTOS) are designed. In this paper, real-fast and real-time performance of RTOS and GPOS are compared when simulating models of high complexity with large time steps. This type of applications is usually present in the automotive industry and requires a good trade-off between real-fast and real-time performance. The performance of an RTOS and a GPOS is compared by running a tire model scalable on the number of degrees-of-freedom and parallel threads. The benchmark shows that the GPOS present better performance in real-fast runs but worse in real-time due to nonexplicit task switches and to the latency associated with interprocess communication (IPC) and task switch.

FPGA Based Single Chip Solution with 1-Wire Protocol for the Design of Smart Sensor Nodes

Applications that involve monitoring of water quality parameters require measuring devices to be placed at different geographical locations but are controlled centrally at a remote site. The measuring devices in such applications need to be small, consume low power, and must be capable of local processing tasks facilitating the mobility to span the measuring area in a vast geographic area. This paper presents the design of a generalized, low-cost, reconfigurable, reprogrammable smart sensor node using a ZigBee with a Field-Programmable Gate Array (FPGA) that embeds all processing and communication functionalities based on the IEEE 1451 family of standards. Design of the sensor nodes includes processing and transducer control functionalities in a single core increasing the speedup of processing power due to interprocess communication taking place within the chip itself. Results obtained by measuring the pH value and temperature of water samples verify the performance of the proposed sensor node.

A parallel Crank–Nicolson finite difference method for time-fractional parabolic equation

Abstract- In this paper, a parallel Crank-Nicolson finite difference method (C-N-FDM) for time-fractional parabolic equation on a distributed system using MPI is investigated. The fractional derivative is described in the Caputos sense. The resultant large system of equations is studied using preconditioned conjugate gradient method (PCG), with the implementation of cluster computing on it. The proposed approach fulfills the suitability for the implementation on Linux PC cluster through the minimization of inter-process communication. To examine the efficiency and accuracy of the proposed method, numerical test experiment using different number of nodes of the Linux PC cluster is studied. The performance metrics clearly show the benefit of using the proposed approach on the Linux PC cluster in terms of execution time reduction and speedup with respect to the sequential running in a single PC.