Intel X86 Architecture Research Articles

Automatic Detection and Decryption of AES Using Dynamic Analysis

In this paper we propose a set of algorithms that can automatically detect the use of AES and automatically recover both the encryption key and the plaintext, assuming that we can control the code flow of the encrypting program, e.g., when an application is performing encryption without the user’s permission. The first algorithm makes use of the fact that we can monitor accesses to the AES S-Box and deduce the desired data from these accesses; the approach is suitable to software-based AES implementations, both naïve and optimized. To demonstrate the feasibility of this approach we designed a tool which implements the algorithm for Microsoft Windows running on the Intel x86 architecture. The tool has been successfully tested against a set of applications using different cryptographic libraries and common user applications. We also discuss the options of recovering the same data when hardware-assisted AES implementations on Intel-compatible architectures are used.

Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores

Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment of its available features that are relevant for the consistency semantics of multi-threaded programs as well as the persistency semantics of programs interfacing with non-volatile memory. We extend these formalisations to cover: (1) non-temporal writes, which provide higher performance and are used to ensure that updates are flushed to memory; (2) reads and writes to other Intel-x86 memory types, namely uncacheable, write-combined, and write-through; as well as (3) the interaction between these features. We develop our formal model in both operational and declarative styles, and prove that the two characterisations are equivalent. We have empirically validated our formalisation of the consistency semantics of these additional features and their subtle interactions by extensive testing on different Intel-x86 implementations.

Deciding reachability under persistent x86-TSO

We address the problem of verifying the reachability problem in programs running under the formal model Px86 defined recently by Raad et al. in POPL'20 for the persistent Intel x86 architecture. We prove that this problem is decidable. To achieve that, we provide a new formal model that is equivalent to Px86 and that has the feature of being a well structured system. Deriving this new model is the result of a deep investigation of the properties of Px86 and the interplay of its components.

Development of ATmega 328P micro-controller emulator for educational purposes

Abstract The paper presents some of our recent results in the field of computer emulation for supporting and enhancing the educational processes. The ATmega 328P micro-controller emulator has been developed as a set of emuStudio emulation platform extension modules (plug-ins). The platform is used at the Department of Computers and Informatics as a studying and teaching support tool. Within the Assembler course, currently, the Intel 8080 architecture and language is briefly described as a preliminary preparation material for the study of Intel x86 architecture, and the Intel 8080 emuStudio emulator module is used here. The aim of this work is to explore the possibility to enrich the course by introducing a more up-to-date and relevant technology and the ATmega is the heart of Arduino – a popular hardware and software prototyping platform. We consider the options to make the process of studying the assembly language principles more attractive for students and using the ATmega AVR architecture, which is broadly deployed in embedded systems, seems to be one of them.

Persistency semantics of the Intel-x86 architecture

Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of RAM. To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the persistency semantics of the ubiquitous x86 architecture remains unexplored to date. To close this gap, we develop the Px86 (‘persistent x86’) model, formalising the persistency semantics of Intel-x86 for the first time. We formulate Px86 both operationally and declaratively, and prove that the two characterisations are equivalent. To demonstrate the application of Px86, we develop two persistent libraries over Px86: a persistent transactional library, and a persistent variant of the Michael–Scott queue. Finally, we encode our declarative Px86 model in Alloy and use it to generate persistency litmus tests automatically.

A volatile-by-default JVM for server applications

A *memory consistency model* (or simply *memory model*) defines the possible values that a shared-memory read may return in a multithreaded programming language. Choosing a memory model involves an inherent performance-programmability tradeoff. The Java language has adopted a *relaxed* (or *weak*) memory model that is designed to admit most traditional compiler optimizations and obviate the need for hardware fences on most shared-memory accesses. The downside, however, is that programmers are exposed to a complex and unintuitive semantics and must carefully declare certain variables as `volatile` in order to enforce program orderings that are necessary for proper behavior. This paper proposes a simpler and stronger memory model for Java through a conceptually small change: *every* variable has `volatile` semantics by default, but the language allows a programmer to tag certain variables, methods, or classes as `relaxed` and provides the current Java semantics for these portions of code. This *volatile-by-default* semantics provides *sequential consistency* (SC) for all programs by default. At the same time, expert programmers retain the freedom to build performance-critical libraries that violate the SC semantics. At the outset, it is unclear if the `volatile`-by-default semantics is practical for Java, given the cost of memory fences on today's hardware platforms. The core contribution of this paper is to demonstrate, through comprehensive empirical evaluation, that the `volatile`-by-default semantics is arguably acceptable for a predominant use case for Java today -- server-side applications running on Intel x86 architectures. We present VBD-HotSpot, a modification to Oracle's widely used HotSpot JVM that implements the `volatile`-by-default semantics for x86. To our knowledge VBD-HotSpot is the first implementation of SC for Java in the context of a modern JVM. VBD-HotSpot incurs an average overhead versus the baseline HotSpot JVM of 28% for the Da Capo benchmarks, which is significant though perhaps less than commonly assumed. Further, VBD-HotSpot incurs average overheads of 12% and 19% respectively on standard benchmark suites for big-data analytics and machine learning in the widely used Spark framework.

Multiprocessor platform for partitioned real-time systems

Two current trends in the real-time and embedded systems are the multiprocessor architectures and the partitioning technology that enables several isolated applications with different criticality levels to share the same computer. This paper presents a real-time platform for multiprocessor and partitioned systems, in which communication requirements are also considered. The paper describes the adaptation of MaRTE OS a monoprocessor real-time operating system to the XtratuM hypervisor for the multiprocessor Intel x86 architecture. This adaptation makes two contributions to ease the development process of future mixed-criticality applications: firstly, it integrates the hypervisor technology and the fully partitioned scheduling in a multiprocessor environment, and secondly, it provides the basis to interconnect partitioned and non-partitioned applications via a homogeneous communication subsystem. Copyright © 2016 John Wiley & Sons, Ltd.

Multiprocessor Ada platform based on MaRTE OS and GNAT

This paper presents the implementation of a multiprocessor Ada platform based on MaRTE OS and GNAT. The paper describes the modifications required to adapt MaRTE OS to a multiprocessor architecture, namely the protection of the internal data structures against concurrent access and the management of several ready queues. We also describe the adaptation of the GNAT run-time library in order to be used on top of the multiprocessor services provided by MaRTE OS. The developed MaRTE/GNAT platform provides full Ada tasking functionality and the multiprocessor support defined in the Ravenscar profile. Two multiprocessor architectures are supported: the multiprocessor version of the XtratuM hypervisor for Intel x86 architecture and the Linux operating system (with MaRTE taking the role of a Pthreads multiprocessor library).

Application execution path analysis for the automatic parallelisation of binary codes in the Intel x86 platform

Traditionally, computer programs have been developed using the sequential programming paradigm. With the advent of parallel computing systems, such as multicore processors and distributed environments, the sequential paradigm became a barrier to the utilisation of the available resources, since the program is restricted to a single processing unit. To address this issue, we propose a transparent automatic parallelisation tool with a binary rewriter. The steps of our approach are: the disassembly of the Intel x86 application, its transformation into an intermediary language; the analysis of this intermediary representation to obtain the flow and dependency graphs; the partitioning of the application into parallel units, using the obtained graphs; and, finally, the reassembly of the application back into the original Intel x86 architecture. By transforming the compiled application software, we aim at obtaining a program which can better explore the parallel resources, with no extra effort required from users or developers.

Techniques and tools for measuring energy efficiency of scientific software applications

The scale of scientific High Performance Computing (HPC) and High Throughput Computing (HTC) has increased significantly in recent years, and is becoming sensitive to total energy use and cost. Energy-efficiency has thus become an important concern in scientific fields such as High Energy Physics (HEP). There has been a growing interest in utilizing alternate architectures, such as low power ARM processors, to replace traditional Intel x86 architectures. Nevertheless, even though such solutions have been successfully used in mobile applications with low I/O and memory demands, it is unclear if they are suitable and more energy-efficient in the scientific computing environment. Furthermore, there is a lack of tools and experience to derive and compare power consumption between the architectures for various workloads, and eventually to support software optimizations for energy efficiency. To that end, we have performed several physical and software-based measurements of workloads from HEP applications running on ARM and Intel architectures, and compare their power consumption and performance. We leverage several profiling tools (both in hardware and software) to extract different characteristics of the power use. We report the results of these measurements and the experience gained in developing a set of measurement techniques and profiling tools to accurately assess the power consumption for scientific workloads.

A LAMMPS implementation of volume–temperature replica exchange molecular dynamics

A driver module for executing volume–temperature replica exchange molecular dynamics (VTREMD) was developed for the LAMMPS package. As a patch code, the VTREMD module performs classical molecular dynamics (MD) with Monte Carlo (MC) decisions between MD runs. The goal of inserting the MC step was to increase the breadth of sampled configurational space. In this method, states receive better sampling by making temperature or density swaps with their neighboring states. As an accelerated sampling method, VTREMD is particularly useful to explore states at low temperatures, where systems are easily trapped in local potential wells. As functional examples, TIP4P/Ew and TIP4P/2005 water models were analyzed using VTREMD. The phase diagram in this study covered the deeply supercooled regime, and this test served as a suitable demonstration of the usefulness of VTREMD in overcoming the slow dynamics problem. To facilitate using the current code, attention was also paid on how to optimize the exchange efficiency by using grid allocation. VTREMD was useful for studying systems with rough energy landscapes, such as those with numerous local minima or multiple characteristic time scales. Program summaryProgram title: vttemperCatalogue identifier: AEVB_v1_0Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEVB_v1_0.htmlProgram obtainable from: CPC Program Library, Queen’s University, Belfast, N. IrelandLicensing provisions: GNU General Public License, version 3No. of lines in distributed program, including test data, etc.: 49706No. of bytes in distributed program, including test data, etc.: 1249424Distribution format: tar.gzProgramming language: C++/MPI.Computer: Tested on Intel X86 and AMD64 architectures. Should be operational on any computer with a C++ compiler.Operating system: Tested on Linux. Should run on any platform with C++ and MPI library.Has the code been vectorized or parallelized?: Yes. 1 to N processors may be used.RAM: Depends on the system size and how the program is partitioned.Classification: 16.13.External routines: LAMMPS (http://lammps.sandia.gov)Nature of problem: The code implements volume–temperature replica exchange molecular dynamics for LAMMPS. Each replica has its own temperature and density. A two-dimensional temperature–density grid is constructed.Solution method: Extending the ability of the existing temper command in LAMMPS to handle replicas of two state variables.Restrictions: The code is based on LAMMPS. A well-designed grid on temperature and density is required.Running time: Running time depends on the system size and the complexity of the problem. Using 8 processors the test run takes approximately 1 minute.

Use of checkpoint-restart for complex HEP software on traditional architectures and Intel MIC

Process checkpoint-restart is a technology with great potential for use in HEP workflows. Use cases include debugging, reducing the startup time of applications both in offline batch jobs and the High Level Trigger, permitting job preemption in environments where spare CPU cycles are being used opportunistically and efficient scheduling of a mix of multicore and single-threaded jobs. We report on tests of checkpoint-restart technology using CMS software, Geant4-MT (multi-threaded Geant4), and the DMTCP (Distributed Multithreaded Checkpointing) package. We analyze both single- and multi-threaded applications and test on both standard Intel x86 architectures and on Intel MIC. The tests with multi-threaded applications on Intel MIC are used to consider scalability and performance. These are considered an indicator of what the future may hold for many-core computing.

Cell Accelerated Cryoablation Simulation

Tumor cryoablation is a clinical procedure where supercooled probes are used to destroy cancerous lesions. Cryoablation is a safe and effective palliative treatment for skeletal metastases, providing immediate and long term pain relief, increasing mobility and improving quality of life. Ideally, lesions are encompassed by an ice ball and frozen to a sufficiently low temperature to ensure cell death. “Lethal ice” is the term used to describe regions within the ice ball where cell death occurs. Failure to achieve lethal ice in all portions of a lesion may explain the high recurrence rate currently observed. Tracking growth of lethal ice is critical to success of percutaneous ablations, however, no practical methods currently exist for non-invasive temperature monitoring. Physicians lack planning tools which provide accurate estimation of the ice formation. Simulation of ice formation, while possible, is computationally demanding and too time consuming to be of clinical utility. We developed the computational framework for the simulation, acceleration strategies for multicore Intel x86 and IBM Cell architectures, and performed preliminary validation of the simulation. Our results demonstrate that the streaming SIMD implementation has better performance and scalability. Both accelerated and non-accelerated algorithms demonstrate good agreement between simulation and manually identified ice ball boundaries in phantom and patient images. Our results show promise for the development of novel cryoablation planning tools with real-time monitoring capability for clinical use.

Coding coarse grained polymer model for LAMMPS and its application to polymer crystallization

We present a patch code for LAMMPS to implement a coarse grained (CG) model of poly(vinyl alcohol) (PVA). LAMMPS is a powerful molecular dynamics (MD) simulator developed at Sandia National Laboratories. Our patch code implements tabulated angular potential and Lennard-Jones-9-6 (LJ96) style interaction for PVA. Benefited from the excellent parallel efficiency of LAMMPS, our patch code is suitable for large-scale simulations. This CG-PVA code is used to study polymer crystallization, which is a long-standing unsolved problem in polymer physics. By using parallel computing, cooling and heating processes for long chains are simulated. The results show that chain-folded structures resembling the lamellae of polymer crystals are formed during the cooling process. The evolution of the static structure factor during the crystallization transition indicates that long-range density order appears before local crystalline packing. This is consistent with some experimental observations by small/wide angle X-ray scattering (SAXS/WAXS). During the heating process, it is found that the crystalline regions are still growing until they are fully melted, which can be confirmed by the evolution both of the static structure factor and average stem length formed by the chains. This two-stage behavior indicates that melting of polymer crystals is far from thermodynamic equilibrium. Our results concur with various experiments. It is the first time that such growth/reorganization behavior is clearly observed by MD simulations. Our code can be easily used to model other type of polymers by providing a file containing the tabulated angle potential data and a set of appropriate parameters. Program summary Program title: lammps-cgpva Catalogue identifier: AEDE_v1_0 Program summary URL: http://cpc.cs.qub.ac.uk/summaries/AEDE_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: GNU's GPL No. of lines in distributed program, including test data, etc.: 940 798 No. of bytes in distributed program, including test data, etc.: 12 536 245 Distribution format: tar.gz Programming language: C++/MPI Computer: Tested on Intel-x86 and AMD64 architectures. Should run on any architecture providing a C++ compiler Operating system: Tested under Linux. Any other OS with C++ compiler and MPI library should suffice Has the code been vectorized or parallelized?: Yes RAM: Depends on system size and how many CPUs are used Classification: 7.7 External routines: LAMMPS ( http://lammps.sandia.gov/), FFTW ( http://www.fftw.org/) Nature of problem: Implementing special tabular angle potentials and Lennard-Jones-9-6 style interactions of a coarse grained polymer model for LAMMPS code. Solution method: Cubic spline interpolation of input tabulated angle potential data. Restrictions: The code is based on a former version of LAMMPS. Unusual features.: Any special angular potential can be used if it can be tabulated. Running time: Seconds to weeks, depending on system size, speed of CPU and how many CPUs are used. The test run provided with the package takes about 5 minutes on 4 AMD's opteron (2.6 GHz) CPUs.

Implementing an applet system without fixing virtual‐machine designs

AbstractAn applet is program code which is downloaded dynamically from a server on the World Wide Web and which can be executed while maintaining security on the client side. The majority of applet systems at present, as represented by the Java Applet, implement the applets using virtual machine code which is independent of computer architecture. This is advantageous in terms of installation and use in different machine environments. Because virtual machine code is associated with execution by an interpreter or conversion to native code, the design of the virtual machine code greatly impacts performance during execution. Normally, however, representation of virtual machine code is fixed for each applet system and cannot be altered. The authors focused on the independence of virtual machine code and implementing an applet execution environment which is independent of the design of virtual machine code by making the Just‐In‐Time (JIT) compiler which converts virtual machine code to native code mobile. In this approach, native code conversion modules which are appropriate for the virtual machine code being used in the applet description are downloaded dynamically. In addition, this applet execution environment provides monitoring functions during applet execution so that a native code applet generated from any virtual machine code can be executed safely. The applet execution monitoring mechanism allows for the programming of system control policies for users, and allows for flexible applet execution control for various levels of monitoring. In this paper, the authors describe an implementation using their newly designed virtual machine code representation in both the SPARC and Intel x86 architecture environments, as well as experiments using this implementation. © 2003 Wiley Periodicals, Inc. Syst Comp Jpn, 34(2): 32–42, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10013

Information Security in Multiprocessor Systems Based on the X86 Architecture

This paper examines security in systems based on Intel x86 architecture and covers aspects from timing attacks to the prevention of service bugs. It reviews some software protection techniques and introduces some new techniques focused on multiprocessor systems.

Integrating segmentation and paging protection for safe, efficient and transparent software extensions

The trend towards extensible software architectures and component-based software development demands safe, efficient, and easy-to-use extension mechanisms to enforce protection boundaries among software modules residing in the same address space. This paper describes the design, implementation, and evaluation of a novel intra-address space protection mechanism called Palladium, which exploits the segmentation and paging hardware in the Intel X86 architecture and efficiently supports safe kernel-level and user-level extensions in a way that is largely transparent to programmers and existing programming tools. Based on the considerations on ease of extension programming and systems implementation complexity, Palladium uses different approaches to support user-level and kernel-level extension mechanisms. To demonstrate the effectiveness of the Palladium architecture, we built a Web server that exploits the user-level extension mechanism to invoke CGI scripts as local function calls in a safe way, and we constructed a compiled network packet filter that exploits the kernel-level extension mechanism to run packet-filtering binaries safely inside the kernel at native speed. The current Palladium prototype implementation demonstrates that a protected procedure call and return costs 142 CPU cycles on a Pentium 200MHz machine running Linux.

Trends in embedded-microprocessor design

When discussing microprocessors, we tend to think of the Intel x86 architecture and its competitors. Doing so, however, ignores the growing market for embedded microprocessors and controllers, in particular the growing 32 bit embedded processor market. This movement toward longer instruction length may seem strange to developers of brake control systems or washing machines-and, indeed, forecasters predict that eight times more 8 bit than 32 bit embedded processors will ship in 1999. But as demand for more complex handheld and portable applications rises, this trend becomes more understandable. Today's 32 bit embedded processor market includes more than 100 vendors and two dozen instruction set architectures. The article describes what these embedded CPUs are and how the requirements of embedded systems make them different from general purpose CPUs.

Operating system benchmarking in the wake of lmbench

The lmbench suite of operating system microbenchmarks provides a set of portable programs for use in cross-platform comparisons. We have augmented the lmbench suite to increase its flexibility and precision, and to improve its methodological and statistical operation. This enables the detailed study of interactions between the operating system and the hardware architecture. We describe modifications to lmbench, and then use our new benchmark suite, hbench:OS, to examine how the performance of operating system primitives under NetBSD has scaled with the processor evolution of the Intel x86 architecture. Our analysis shows that off-chip memory system design continues to influence operating system performance in a significant way and that key design decisions (such as suboptimal choices of DRAM and cache technology, and memory-bus and cache coherency protocols) can essentially nullify the performance benefits of the aggressive execution core and sophisticated on-chip memory system of a modern processor such as the Intel Pentium Pro.