Intel Threading Building Blocks Research Articles

Parallelization libraries

Creating efficient, scalable dynamic parallel runtime systems for chip multiprocessors (CMPs) requires understanding the overheads that manifest at high core counts and small task sizes. In this article, we assess these overheads on Intel's Threading Building Blocks (TBB) and OpenMP. First, we use real hardware and simulations to detail various scheduler and synchronization overheads. We find that these can amount to 47% of TBB benchmark runtime and 80% of OpenMP benchmark runtime. Second, we propose load balancing techniques such as occupancy-based and criticality-guided task stealing, to boost performance. Overall, our study provides valuable insights for creating robust, scalable runtime libraries.

Multicore Desktop Programming with Intel Threading Building Blocks

The paper mentions that the Intel Threading Building Blocks is a key component of Intel Parallel Building Blocks. This widely used C++ template library helps developers achieve well-performing modular parallel programs in multiprogrammed environments.

Application of parallel ant colony algorithm based on TBB and Cilk++ in path optimization

An Ant Colony Algorithm (ACA) with rollback mechanism was proposed for obtaining optimized path,which traverses all necessary nodes in real road network.In case of the large scale real road network,the convergence speed of traditional sequential ACA was quite slow.Therefore,two parallel ACAs based on Intel Threading Building Blocks (TBB) and Cilk++ parallel programming model were designed separately.Both of them were easier to operate with simple instructions than complicated thread triggering and critical resource boundary recognition.Therefore,these two models were easier to develop and more applicable compared with WinAPI multi-threaded based parallel ACA (pACA).The experimental results show that pACA based TBB is nearly identical with pACA based on WinAPI in terms of efficiency,while pACA based on Cilk++ exhibits higher efficiency and better speed-up than pACA based on WinAPI in dual-core system.

Lazy binary-splitting

We present Lazy Binary Splitting (LBS), a user-level scheduler of nested parallelism for shared-memory multiprocessors that builds on existing Eager Binary Splitting work-stealing (EBS) implemented in Intel's Threading Building Blocks (TBB), but improves performance and ease-of-programming. In its simplest form (SP), EBS requires manual tuning by repeatedly running the application under carefully controlled conditions to determine a stop-splitting-threshold (sst) for every do-all loop in the code. This threshold limits the parallelism and prevents excessive overheads for fine-grain parallelism. Besides being tedious, this tuning also over-fits the code to some particular dataset, platform and calling context of the do-all loop, resulting in poor performance portability for the code. LBS overcomes both the performance portability and ease-of-programming pitfalls of a manually fixed threshold by adapting dynamically to run-time conditions without requiring tuning. We compare LBS to Auto-Partitioner (AP), the latest default scheduler of TBB, which does not require manual tuning either but lacks context portability, and outperform it by 38.9% using TBB's default AP configuration, and by 16.2% after we tuned AP to our experimental platform. We also compare LBS to SP by manually finding SP's sst using a training dataset and then running both on a different execution dataset. LBS outperforms SP by 19.5% on average. while allowing for improved performance portability without requiring tedious manual tuning. LBS also outperforms SP with sst=1 , its default value when undefined, by 56.7%, and serializing work-stealing (SWS), another work-stealer by 54.7%. Finally, compared to serializing inner parallelism (SI) which has been used by OpenMP, LBS is 54.2% faster.

VERTAF/Multi‐Core: A sysml‐based application framework for multi‐core embedded software development

Multi‐core processors are becoming prevalent rapidly in personal computing and embedded systems. Nevertheless, the programming environment for multi‐core processor based systems is still quite immature and lacks efficient tools. In this paper, we present a new VERTAF/Multi‐Core framework and show how software code can be automatically generated from SysML models of multi‐core embedded systems. We illustrate how model‐driven design based on SysML can be seamlessly integrated with Intel's threading building blocks (TBB) and the Quantum Platform middleware. We use a digital video recording system to illustrate the benefits of the framework. Our experiments show how SysML/QF/TBB help in making the multi‐core embedded system programming model‐driven, easy, efficient, and effortless.

Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors

With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computing systems. Many issues of parallelism management boil down to discerning which running threads or processes are critical, or slowest, versus which are non-critical. If one can accurately predict critical threads in a parallel program, then one can respond in a variety of ways. Possibilities include running the critical thread at a faster clock rate, performing load balancing techniques to offload work onto currently non-critical threads, or giving the critical thread more on-chip resources to execute faster. This paper proposes and evaluates simple but effective thread criticality predictors for parallel applications. We show that accurate predictors can be built using counters that are typically already available on-chip. Our predictor, based on memory hierarchy statistics, identifies thread criticality with an average accuracy of 93% across a range of architectures. We also demonstrate two applications of our predictor. First, we show how Intel's Threading Building Blocks (TBB) parallel runtime system can benefit from task stealing techniques that use our criticality predictor to reduce load imbalance. Using criticality prediction to guide TBB's task-stealing decisions improves performance by 13-32% for TBB-based PARSEC benchmarks running on a 32-core CMP. As a second application, criticality prediction guides dynamic energy optimizations in barrier-based applications. By running the predicted critical thread at the full clock rate and frequency-scaling non-critical threads, this approach achieves average energy savings of 15% while negligibly degrading performance for SPLASH-2 and PARSEC benchmarks.

Intel threading building blocks

Intel Threading Building Blocks [1] is a C++ runtime library that abstracts the low-level threading details necessary for effectively utilizing multi-core processors. It uses C++ templates to elimi...

The Foundations for Scalable Multicore Software in Intel Threading Building Blocks

The Foundations for Scalable Multicore Software in Intel Threading Building Blocks