Deep silicon etching is typically used in applications requiring high aspect ratio structures, like MEMS devices or 3D integration in microelectronics. In this last case, the most common technologies are Through-Silicon-Vias (TSV), used as electrical interconnects for die stacks in 3D packaging, and 3D capacitors, where very high specific capacities can be reached.The time-multiplexed Bosch process is widely used for deep etching and presents a good reproducibility if cleaning of the chamber is performed periodically. However, the etched structures exhibit polymer contamination, due to C4F8passivation steps, and scalloping, due to the etching-passivation cycles.Cryogenic silicon etching usually improves the etched profiles with smooth sidewalls and no polymer is utilized for passivation. The standard process is based on a silicon substrate cooled at a cryogenic temperature (-120°C to -100°C) and exposed to a monocyclic SF6/O2 plasma. The SiOxFypassivation layer, which prevents lateral etching and thus promotes vertical etching, is stable only at low temperature and is desorbed when heated to room temperature.It is also possible to alternate passivation-etching cycles at cryogenic temperature of the substrate, like the Bosch process. This is the so-called STiGer process. However, the passivation chemistry is different: SiF4/O2 is used instead of C4F8. Like the standard cryogenic process, a SiOxFy passivation film is formed when the substrate is cooled at cryogenic temperature. A SF6 or a SF6/O2plasma can be used for the etching step. Generally, STiGer processes have a better reproducibility and robustness than the standard cryogenic process.Since current trends in microelectronics lead to the shrinking of critical dimensions in pattern transfer, we present in this paper how silicon cryogenic processes can be tuned for downscaling features. Conventional SiO2 masks cannot be easily structured at dimensions down to nanoscale. Several authors have investigated the potentialities of silicon cryogenic etching at the sub-50 nm scale with polymer masks. Polymer masks patterned by means of e-beam lithography is a possibility but Block CoPolymer (BCP) masks have particularly emerged for sub-30 nm features. The main issue is the selectivity between silicon and the polymer mask which is much lower than that of SiO2. In this paper, we present first results of silicon cryoetching using polystyrene masks structured at submicronic scale (down to 300 nm) by blending homopolymers. This is an alternative to BCP masks with a lower cost. Nevertheless, the current control of the hole diameter distribution is not as accurate as that of BCP and as a result, there are different diameters on the same mask. The process was developed using onset of black silicon formation. These light-absorbing structures, which appear in over-passivating regime, have a submicronic characteristic diameter. If the features to be etched have a characteristic dimension of the same order of magnitude, black silicon does not appear. With etching conditions just above the limit of black silicon onset, it is possible to etch anisotropic profiles with vertical sidewalls and minimal defects. Holes have been etched with such a process. The smaller features are 300 nm in diameter and 2.1 µm deep (etch rate of 2.5 µm/min), which represents an aspect ratio of 7. The selectivity of the polystyrene mask is (31:1). Two alternative masks have also been tested to increase the selectivity. First, porous polymer films have been replicated into SiO2 replicas to produce patterned hard silica masks at reduced scale. Secondly, a staining of polymer masks has been tested. We will present and compare both profiles and performances of polymeric masks and their alternatives.
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Open Access
Jun 1, 2017
Daniel J Thomas + 3
