Integration Of Intellectual Property Research Articles

The Frictions of IP and the Schism in Turkey’s Collective Management of Music Copyright

Despite the increasing international integration of intellectual property (IP), national laws and structures for implementing rights in music continue to vary, for better or for worse, in ways that matter to musicians and other copyright stakeholders. This article draws on oral history and archival data to examine one such variation. Where most countries have only one copyright collecting society for musical authors, there are two in Turkey (MESAM and MSG). IP experts and administrators blame competition or lack of coordination between the two societies for a host of problems, including complicating the processes of performing rights licensing and royalty distribution. Analyzing the origin story of the second collecting society through the lens of Anna Tsing’s influential concept of “friction,” I highlight the social and cultural dynamics that complicate the ongoing global integration of IP and the general development of structures for enforcing IP rights in music.

Patents, trade and medicines: past, present and future

This article analyzes the spread of intellectual property in trade agreements. We explain how the integration of intellectual property with international trade rules led to the globalization of pharmaceutical patenting, and then how additional provisions related to pharmaceutical products have been introduced by regional and bilateral trade agreements. We describe the additional ‘TRIPS-Plus’ rules contained in recent trade agreements, which go beyond the requirements of the World Trade Organization’s TRIPS Agreement, and explain the potential challenges that they may create for developing countries. We draw attention to the conceptual and methodological challenges of assessing the effects of patent provisions in trade agreements on prices and access to drugs, with particular emphasis on the importance of timing. Depending on when countries began allowing drugs to be patented, TRIPS-Plus provisions have different effects; and when pharmaceutical patenting has been in place for more countries for more time, the effects of TRIPS-Plus provisions will change again.

Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCs

In modern system-on-chip (SoC) designs, IP-reuse is considered a driving force to increase productivity. To support various designs, a huge amount of Intellectual Property (IP) hardware blocks have been developed. The integration of those IPs into an SoC may require significant effort—up to days or weeks depending on experience and complexity. This article presents a novel approach to significantly reduce the design effort to bring-up a working SoC design by automatic IP integration as part of a library-based Software-defined SoC flow. In detail, the IP-supplier prepares a HW-accelerated software library (HASL) for the SoC architect, who wants to use the IP in an SoC design. As a key point of our approach, integration knowledge is encoded in the library as a set of integration rules. These rules are defined in the machine-readable standardized IP-XACT format by the IP supplier, who has a good knowledge of the IP’s hardware details. The library preparation step on the IP supplier’s side is also partly automated in the proposed flow, including a partial generation of configurable HW drivers, schedulers, and the software library functions. For the SoC architect, we have developed the graph-grammar-based IP-integration (GRIP) tool. The software application is developed using the functions supplied in the HASL. According to the calls to the HASL functions, the GRIP tool automatically integrates IP-blocks using the rule information supplied with the library and runs a full Design Space Exploration. For this, the SoC architecture and rules are transformed into the graph domain to apply graph rewriting methods. The GRIP tool is model-driven and based on the Eclipse Modeling Framework. With code generation techniques, SoC candidate architectures can be transformed to hardware descriptions for the target platform. The HW/SW interfaces between SW library functions and IP blocks can be automatically generated for bare-metal or Linux-based applications. The approach is demonstrated with two case-studies on the Xilinx Zynq-based ZedBoard evaluation board using a HASL for computer vision. It can yield 10×-150× performance improvement for the bare-metal application versions and 4×--7× performance improvement for the Linux-based application versions, when executed on an optimized HW-accelerated SoC architecture compared to a non HW-accelerated SoC. The effort for IP integration is comparable to using a software library, hence, providing a significant advantage over a manual IP integration.

Constructing A Model Intellectual Property Policy for Development in Nigeria

The construction of a Model policy on intellectual property in Nigeria has become urgent due to the need for reform and advocacy for improvements in developing, protecting and enforcing intellectual property rights (IPRs) in Nigeria. This paper proposes a bottom up approach in adopting the appropriate Model policy. This approach prioritizes the needs of the people regarding intellectual properties based on western and traditional knowledge systems in Nigeria. The integration of intellectual property into the economic development plans of Nigeria through policies will indeed assist in reducing poverty, helping to combat diseases, improving health, enhancing access to education and contributing to sustainable development.

A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection

Design fingerprinting is a means to trace the illegally redistributed intellectual property (IP) by creating a unique IP instance with a different signature for each user. Existing fingerprinting techniques for hardware IP protection focus on lowering the design effort to create a large number of different IP instances without paying much attention on the ease of fingerprint detection upon IP integration. This paper presents the first dynamic fingerprinting technique on sequential circuit IPs to enable both the owner and legal buyers of an IP embedded in a chip to be readily identified in the field. The proposed fingerprint is an oblivious ownership watermark independently endorsed by each user through a blind signature protocol. Thus, the authorship can also be proved through the detection of different user's fingerprints without the need to separately embed an identical IP owner's signature in all fingerprinted instances. The proposed technique is applicable to both application-specific integrated circuit and field-programmable gate array IPs. Our analyses show that the fingerprint is immune to collusion attack and can withstand all perceivable attacks, with a lower probability of removal than state-of-the-art FSM watermarking schemes. The probability of coincidence of a 32-bit fingerprint is in the order of 10-10 and up to 1035 32-bit fingerprinted instances can be generated for a small design of 100 flip-flops.

Intellectual property management in M&A transactions

Purpose – The purpose of this paper is to focus on the intellectual property (IP) aspects of mergers and acquisitions (M&A) transactions.Design/methodology/approach – A holistic approach is proposed that embraces IP as an integral part of the M&A process in the form of a roadmap for the strategic and purposeful management of IP assets in M&A deals.Findings – Addressing IP issues in transactions in isolation can lead to undesirable consequences (e.g. considerable costs for unplanned purchases of rights). IP due diligence and IP integration project processes can be automated using collaborative software solutions. Thereby, risk can be reduced through the creation of a high level of transparency and predefined responsibilities.Practical implications – Although the proposed IP management framework is based on intellectual property matters relevant to German jurisdiction, conclusions derived and the proposed roadmap are transferable to other jurisdictions and hence have a broader relevance. Evidence for this i...

MCF: A Metamodeling-Based Component Composition Framework—Composing SystemC IPs for Executable System Models

Reusing Intellectual Property (IP)-cores accompanied by automated generation of the glue-logic, and automated composability checks can help designers to create efficient system-level models quickly and correctly for fast design space exploration. Furthermore, with the rise of multiple transaction level and register-transfer level abstractions, constructing models with mixed abstraction levels is also important. A framework that allows designers to: 1) describe the structure of components, their interfaces, and their interactions, with a semantically rich visual frontend; 2) automatically select IPs from a component library-based on sound-type theoretic principles; and 3) perform constraint based checks for composability, is highly desirable in this context. A metamodel based framework brings forth further advantages. It helps in: 1) providing rigorous semantics to the visual models; 2) imposing restrictions on the model and on interactions between components through constraints expressed in a constraint language; and 3) enabling type-checking and inference-based facilities. Furthermore, using XML-based schemas to store and process meta-information about the IPs as well as the schematic visual model, allows for an IP selection and integration methodology using existing XML processing tools. With these in mind, we present MCF, a metamodeling-based component composition framework for SystemC-based IP core composition at multiple and mixed abstraction levels, with all the advantages stated above.

System-on-Chip: Reuse and Integration

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

Recent developments in Japan’s intellectual property industry

There have been many changes and new initiatives in the field of intellectual property (IP) and the use of patent information (PI) in Japan in recent years. In this article the author provides a concise survey of these developments. Topics embraced include the increased corporate emphasis on IP and the moves towards greater integration of IP and PI into other core activities such as R & D and strategic planning. Japanese government initiatives covered include the Intellectual Property Policy Outline and the Intellectual Property Strategic Program, as well as major efforts to reduce backlogs of patent applications awaiting search and examination—such as outsourcing and the increased recruitment of examiners. Other topics referred to include the increasing need for better prior art searches early in the R & D process, patent databases and licensing activities.

Intellectual Property Rights and the Commodity Form: New Dimensions in the Legislated Transfer of Surplus Value

Intellectual property rights have become an integral part of the modern economy. This article analyzes some of the contradictions of intellectual property rights and suggests a direction for the integration of intellectual property into classical value theory.

A formal approach to mpsoc performance verification

Multiprocessor system on chip designs use complex on-chip networks to integrate different programmable processor cores, specialized memories, and other components on a single chip. MpSoC have been become the architecture of choice in many industries. Their heterogeneity inevitably increases with intellectual-property integration and component specialization. System integration is becoming a major challenge in their design. Simulation is state of the art in MpSoC performance verification, but it has conceptual disadvantages that become disabling as complexity increases. Formal approaches offer a systematic alternative. The article presents a technology that uses event model interfaces and a novel event flow mechanism that extends formal analysis approaches from real-time system design into the multiprocessor system on chip domain.

Cost and performance analysis for mixed-signal system implementation: system-on-chip or system-on-package?

Advances in integrated circuits and packaging technologies provided us more implementation options for mixed-signal systems. Emerging technologies are represented by system-on-chip (SoC) and system-on-package (SoP). In order to make a design decision for optimal system implementation, it is hence becoming more and more important to address the cost and performance issues for various implementation options early in a system deign phase. In this paper, we develop a modeling technique for a priori cost and performance estimations for mixed-signal system implementations. The performance model evaluates various noise isolation technologies, such as using guard rings, increasing the separation between digital and analog/RF circuitry parts, using special substrate materials (e.g., silicon-on-insulator), and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or virtual components, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, are considered. Finally, an efficient computation algorithm, namely COMSI, was developed for cost estimation under various mixed-signal performance constraints. Case studies for SoC and SoP integration are performed using COMSI.

Intellectual Property in International Relations

This article explores how the integration of intellectual property in international relations could facilitate the transfer of technology from the North to the South. The role of technical and development cooperation among countries is imperative to international relations. International relations enhance cooperation among countries and make possible the inflow and outflow of capital goods and services among cooperating countries. Today, people think about the North as having control over advanced technologies revolving around intellectual property, which deals with specialized issues and which is governed by such specialized branches of law as industrial property law and copyright law. Considering the fact that issues pertaining to technologies are invariably an integral part of any policy designed to achieve sustainable development at all levels, integrating intellectual property discussion in international relations could facilitate acquisition of expired patents by developing countries for accelerated expansion of their social construction.