InP Integration Research Articles

Electrically pumped InP-based microdisk lasers integrated with a nanophotonic silicon-on-insulator waveguide circuit

A compact, electrically driven light source integrated on silicon is a key component for large-scale integration of electronic and photonic integrated circuits. Here we demonstrate electrically injected continuous-wave lasing in InP-based microdisk lasers coupled to a sub-micron silicon wire waveguide, fabricated through heterogeneous integration of InP on silicon-on-insulator (SOI). The InP-based microdisk has a diameter of 7.5 mum and a thickness of 1 mum. A tunnel junction was incorporated to efficiently contact the p-side of the pn-junction. The laser emits at 1.6 mum, with a threshold current as low as 0.5 mA under continuous-wave operation at room temperature, and a threshold voltage of 1.65 V. The SOI-coupled laser slope efficiency was estimated to be 30 muW/mA, with a maximum unidirectional output power of 10 muW.

Low temperature InP layer transfer onto Si by helium implantation and direct wafer bonding

Helium implantation-induced layer splitting of InP in combination with direct wafer bonding was utilized to achieve low temperature layer transfer of InP onto Si(1 0 0) substrates. InP(1 0 0) wafers with 4 inch diameter were implanted by 100 keV helium ions with a dose of 5 × 1016 cm−2. Then the as-implanted wafers were coated with a spin-on glass (SOG) oxide having a thickness of 150 nm. The SOG coated InP wafers were subsequently bonded to thermally oxidized Si(1 0 0) handle wafers and the bonded wafer pairs were annealed at 200 °C for 20 h to achieve InP layer transfer onto Si(1 0 0) wafers, enabling monolithic integration of InP with Si. Cross-sectional transmission electron microscope images of the transferred InP layers revealed that the layers were about 650 nm thick, which consisted of a heavily damaged InP layer about 300 nm thick directly at the surface and a remaining 350 nm thick layer with considerably less damage.

Shrinking transceivers drive InP integration

The shrinking 19Gbit/s transceiver form-factor multi-source agreements-from XENPAK through to X2/XPAK and XFP — are now placing the emphasis increasingly on more compact and much less power hungry components.

Effect of III/V-Compound Epitaxy on Si Metal-Oxide-Semiconductor Circuits

Several approaches to the heteroepitaxial growth of InP on (100)Si employing an electrochemically etched Si mesa, SiO2 masks, and a maskless procedure were investigated with the objective of achieving area-selective InP integration into Si metal-oxide-semiconductor (Si-MOS) technology. Maskless InP/Si device layer growth by metal-organic vapour-phase epitaxy with good selectivity on a structured InP buffer layer, surrounded by oxide, was achieved. Undesired InP depositions were removed with an SiO2 emulsion, spun on prior to InP growth. To study the effects on the Si-based electronics, p-metal-oxide-semiconductor field-effect tansistors (MOSFETs) were exposed to the various stages of the heteroepitaxial InP growth process. We have studied the influence of hydride atmospheres and thermal anneals on their electrical performance. A standard InP-on-(100)Si growth procedure was found to be acceptable for the MOS components, as demonstrated by a Schmitt-trigger laser-diode driver circuit.