Integrated Circuits Research Articles

Micro-Transfer printing of InGaAs/InP Avalanche Photodiode on Si Substrate

Abstract We report on the fabrication and micro-transfer printing of InGaAs/InP avalanche photodiodes (APDs) onto silicon substrates. A process flow was developed to suspend the devices using semiconductor tethers. The developed process reduces the number of fabrication steps required compared to methods based on the use of photoresist tethers. Furthermore, our process is compatible with devices that may be susceptible to damage induced by the photoresist removal process. APDs were characterised in linear mode operation both before suspension and after printing. Despite the additional fabrication steps required to suspend the APD membranes and the physical nature of the micro-transfer printing process, the electrical characteristics of the devices were preserved. No degradation in the optical performance of the devices was measured. Our work represents the first demonstration of micro-transfer printing of InGaAs/InP avalanche photodiodes onto silicon substrates. The results highlight the viability of micro-transfer printing for effective heterogeneous integration of InGaAs/InP avalanche photodiodes with silicon photonic integrated circuits for optical and quantum communication and other light detection applications.

The Model and Simulation of Memristor

Memristor is an emerging electronic component, tremendous efforts have been made in the fields of memristor, motivated by its unique resistor switching feature, as well as the good compatibility with the current integrated circuit (IC) technologies. It has been widely accepted that memristor would be a powerful candidate for constructing the brain-like computing hardware system in the next generation of electronics. Even so, there are still challenges in the development of the memristor IC and the calculation system based on it. For an example, the lack of memristor simulation module hinders its automatic design. Herein, we would like to propose a method for simulating the feature of the memristor. Firstly, based on the conductive filament based physical principle of memristor, calculations are conducted to simulate the basic electronic features of memristor. The good fitness confirms the feasibility of the proposed method. Second, the memristor’s resistance switching feature is modelled by Spice, a popular design platform. With the use of Voltage-Controlled Current Source (VCCS) in Spice, a modulus of memristor is established and executed to simulate the switched resistances under different bias voltages. In summary, this work demonstrates the feasibility of the proposed simulating method, it may provide an easy-to-operate way to improve design efficiency of active memristor arrays

Optimized leakage control in CMOS NAND gates: The In-Triggering technique

Abstract Leakage power, now the largest contributor to integrated circuit power consumption, is rising quickly, according to the International Technology Roadmap for Semiconductors (ITRS). As CMOS (complementary metal-oxide semiconductor) technology continues to shrink to deep submicron levels, gate leakage and subthreshold have become important components that contribute to total power dissipation. To address this problem, many methods have been put forth, especially at the circuit level. In 45 nm CMOS, variability and short-channel effects limit noise margins and compromise gate delays, thereby compromising the timing closure and robustness of ultra-low voltage circuits. The resulting supply voltage guardband may reduce energy efficiency in order to achieve a reasonable production yield. Furthermore, the high leakage currents of these technologies decrease energy efficiency when idle intervals are prolonged. In this study, two designs of a novel two-input NAND gate at 45 nm CMOS technology are constructed using eight transistors (8-T). A novel circuit technique named "In-Triggering (INDEP with Bi-Triggering)" is presented in this study with the goal of lowering subthreshold leakage in digital circuits. This method is thoroughly contrasted with other leakage reduction strategies now in use, such as Base, Sleepy LECTOR, LECTOR, INDEP, and Bi-Triggering procedures. Evaluation is done using key performance measures such power-delay product (PDP), latency, subthreshold leakage power, and total power consumption. 45-nm Predictive Technology Models (PTM) with a nominal supply voltage of 1V are used in the investigation. According to our findings, the suggested In-Triggering technique outperforms the conventional NAND gate in terms of speed by 12% and significantly reduces leakage power by up to 56%. Furthermore, compared to the Base, Trig01, and INDEP NAND gates, the method offers mean power savings of 58.8%, 36.1%, and 30.7%, respectively. At supply voltages of 1V, a comprehensive comparison and verification are then conducted utilizing the several proposed and existing methodologies. The effectiveness of the In-Triggering technique in reducing leakage power in CMOS circuits is confirmed by comparing these results to the most well-known design strategies for both active operation and sleep modes.

Heterogeneous integration of GaInAsSb-GaSb photodiodes on SOI photonic integrated circuits for SWIR applications

Heterogeneous integration of GaInAsSb-GaSb photodiodes on SOI photonic integrated circuits for SWIR applications

Role of Neural Circuits in Cognitive Impairment.

Cognitive impairment refers to abnormalities in learning, memory and cognitive judgment, mainly manifested as symptoms such as decreased memory, impaired orientation and reduced computational ability. As the fundamental unit of information processing in the brain, neural circuits have recently attracted great attention due to their functions in regulating pain, emotion and behavior. Furthermore, a growing number of studies have suggested that neural circuits play an important role in cognitive impairment. Neural circuits can affect perception, attention and decision-making, they can also regulate language skill, thinking and memory. Pathological conditions crucially affecting the integrity and preservation of neural circuits and their connectivity will heavily impact cognitive abilities. Nowadays, technological developments have led to many novel methods for studying neural circuits, such as brain imaging, optogenetic techniques, and chemical genetics approaches. Therefore, neural circuits show great promise as a potential target in mitigating cognitive impairment. In this review we discuss the pathogenesis of cognitive impairment and the regulation and detection of neural circuits, thus highlighting the role of neural circuits in cognitive impairment. Hence, therapeutic agents against cognitive impairment may be developed that target neural circuits important in cognition.

Comparative Analysis of Analogue and Digital Methods for Magnetic Flux Estimation in the Core of a Medium-Voltage Voltage Transformer Operating Under Ferroresonance Conditions

The main objective of the research described in the article was to determine the following: Is it possible to estimate the magnetic flux linkage in the core of a voltage transformer using analogue or digital methods? Will it be possible to estimate it approximately both in the normal state and in the state of deep core saturation (ferroresonant state)? The research aimed to identify the advantages and disadvantages of both proposed estimation methods. As part of the research described in this paper, a simulation model was developed and executed in the MATLAB/Simulink environment to generate a series of secondary voltage and flux waveforms in voltage transformers. The secondary voltage and flux waveforms were modelled under ground fault conditions, initiating ferroresonance oscillations in the medium-voltage network. To determine the associated flux from the simulated secondary voltages of the voltage transformers, an analogue integration circuit, a voltage analogue input circuit and a numerical integration algorithm with offset elimination were developed and implemented in an STM32 microcontroller. The obtained reference flux waveforms were used to verify the accuracy of the estimation of flux waveforms obtained using the analogue and digital methods. As a result, it was determined that both methods allow for a relatively accurate estimation of the periodic component of the magnetic flux. It also presented how both methods respond to the presence of slowly changing (aperiodic) components. Possible applications were proposed in order to create an innovative criterion for detecting ferroresonance oscillations.

Barriers to manufacturing integrated circuit chips in the Indian semiconductor manufacturing industry using the grey influence analysis (GINA)

Barriers to manufacturing integrated circuit chips in the Indian semiconductor manufacturing industry using the grey influence analysis (GINA)

Wake-up free La-doped ZrO2 antiferroelectric capacitors

Abstract This study experimentally investigated La-doped ZrO2 (ZLO) antiferroelectric (AFE) capacitors. Significant polarization enhancement is demonstrated in ZLO antiferroelectric capacitors with the optimized La concentration. The ZLO antiferroelectric capacitors reveal superior performance even under a low-temperature process (< 400℃). Remarkably, without the post-metallization annealing (PMA), ZLO devices still possess excellent antiferroelectric properties, which is highly advantageous for back-end-of-line (BEOL) process. Further endurance testing shows that ZLO antiferroelectric devices could withstand the wake-up effect during cycling process, showcasing unexceptionable endurance (>1010 cycles). The results in this study opens new avenues for practical antiferroelectric applications and brings promise for their integration into advanced integrated circuits.

Enhancement of liner materials based on nanomaterials to promote sustainability in noise intercourse

Daily usage of devices has had a major influence on lives and existence, which would be unimaginable without them. Due to this, recent gadget dependability concerns need particular attention. PCs, hand mobile phones, and other computerized household gadgets need integrated circuits (ICs). Individual components must work together to accomplish their tasks and make the circuit operate. Hot carrier effect, oxide breakdown, and other system-level problems result from accommodating several devices in a planar IC. Vertical linking active components in one IC to another IC is a common method of three-dimensional IC integration (3D-IC). The main issue with 3D-IC adoption is electrical interference to neighboring through silicon via (TSV) and active transistors, which substantially reduces system performance. The electrical TSV (ETSV) model, which employs solely electrical signal carrying TSV, and the thermal TSV (TTSV) model, which incorporates thermal TSV during simulation, are used in this research to reduce electrical interference. The electrical signal transporting TSV to the substrate and other TSV was investigated for interference. With other models, this study also shows higher frequency regimes up to 1 THz. We found that the suggested methodology improves 3D-IC development by more than 30% by reducing electrical interference from signal-carrying TSV to other TSV.

Sequentially amplified integration of catalytic DNA circuits for high-performance intracellular imaging of miRNA and interpretation of mRNA-miRNA signalling pathway

The cascaded catalytic circuits are viable tools for improving the signal gain of biosensors, yet their sensing performance is still limited by the signal leakage from complex biological environment and unsatisfying reaction efficiency from inter-reactants steric hindrance. Herein, we proposed a catalytically localized DNA (CLD) circuit for the accurate and high-efficiency imaging of microRNA (miRNA) in living cells by virtue of the sequentially and successively amplified integration of catalytic DNA circuits. The compact CLD circuit was constructed by integrating two elemental catalytic circuits, cell-responsive EDR module and analyte-sensing CHA module, where CHA module was initially caged in EDR module for eliminating the unwanted off-site and off-target signal leakage. Only by cell-specific messenger RNA (mRNA)-activated EDR operation then the elemental CHA circuit could be successively connected to facilitate the highly efficient intramolecular reaction with low steric hindrance, thus leading to accelerated reaction efficiency for miRNA analyte. The multiple molecular recognition and the spatial self-confinement of the smart CLD circuit enable the accurate and high-efficiency imaging of intracellular miRNA. The interaction network of mRNA and miRNA was then investigated in situ through our CLD circuit, which provides a powerful tool for discovering the underlying signal pathways between these different RNAs in living cells.

Design of Flash analog-to-digital converter based on MoS2 FET

In this paper, we leverage the advantages of MoS2 FETs to design a 4-bit Flash ADC that achieves a reduced active area and dynamic power. The proposed ADC employs a threshold inverter quantization (TIQ) technique to eliminate static power dissipation. A SPICE-compatible charge-based model for MoS2 FETs is used to simulate the proposed ADC. The high ON/OFF current ratio and nanoscale size of MoS2 FETs contribute to a smaller ADC active area and lower dynamic power compared to other technologies. Simulation results indicate a differential nonlinearity (DNL) of [−0.18, 0.12]LSB and an integral nonlinearity (INL) of [−0.32, 0.24]LSB meeting the requirements for 4-bit resolution at a 2 V operating voltage. While the FFT spectrum analysis reveals a signal-to-noise ratio (SNR) of 29.37 dB, the effective resolution bandwidth (ERBW) of 2.2 GHz is obtained, highlighting the ADC’s performance in high-speed applications. Additionally, the low ADC active area of 3000 μm2 makes it suitable for very large-scale integration (VLSI) circuits. The proposed method is sensitive to variations in process, temperature, and power supply voltage, and their effects on ADC performance are also examined.

Suppression of parasitic lasing in erbium doped thin film lithium niobate waveguide amplifier by integrated wavelength division multiplexer

Photonic integrated circuits based erbium doped amplifiers have attracted great interest due to their compact footprint, high gain in the telecom C-band, and high scalability for functional integration. In this work, a wavelength division multiplexer integrated erbium doped waveguide amplifier fabricated on the thin film lithium niobate on insulator platform is demonstrated. An on-chip saturated power of 10 dBm with the net gain around 10 dB is achieved from the monolithically integrated amplifier chip with the footprint of only 3 × 5 mm2. In particular, the suppression of parasitic lasing in the waveguide amplifier is realized thanks to the spectral response of the integrated wavelength division multiplexer. Theoretical analysis of parasitic lasing on amplifier performance is also conducted. The demonstrated integrated erbium doped waveguide amplifier will find great use in various applications based on the thin film lithium niobate on an insulator platform.

Frequency agile photonic integrated external cavity laser

Recent advances in the development of ultra-low loss silicon nitride integrated photonic circuits have heralded a new generation of integrated lasers capable of reaching fiber laser coherence. However, these devices are presently based on self-injection locking of distributed feedback laser diodes, increasing both the cost and requiring tuning of laser setpoints for their operation. In contrast, turn-key legacy laser systems use reflective semiconductor optical amplifiers (RSOAs). While this scheme has been utilized for integrated photonics-based lasers, so far, no cost-effective RSOA-based integrated lasers exist that are low noise and simultaneously feature fast, mode-hop-free, and linear frequency tuning as required for frequency modulated continuous wave (FMCW) LiDAR or for laser locking in frequency metrology. Here we overcome this challenge and demonstrate a RSOA-based, frequency agile integrated laser, that can be tuned with high speed, with high linearity at low power. This is achieved using monolithic integration of piezoelectrical actuators on ultra-low loss silicon nitride photonic integrated circuits in a Vernier filter-based laser scheme. The laser operates at 1550 nm, features a 6 mW output power and a 400 Hz intrinsic laser linewidth, and allows ultrafast wavelength switching within 7 ns rise time and 75 nW power consumption. In addition, we demonstrate the suitability for FMCW LiDAR by showing laser frequency tuning over 1.5 GHz at 100 kHz triangular chirp rate with a nonlinearity of 0.25% after linearization and use the source for measuring a target scene 10 m away with a 8.5 cm distance resolution.

Washability of E‐Textiles: Washing Behavior of Textile Integrated Circuits Depending on Textile Substrate, Circuit Material and Integration Method

AbstractWearable electronic textiles (e‐textiles) can provide comfortable and unobtrusive solutions for a wide range of applications, yet insufficient reliability is preventing a wider market success. Washability is a critical reliability concern, especially for textile integrated circuits that are permanently attached to the textile substrate. A variety of textile circuits on different textile substrates were subjected to up to 100 wash cycles to understand washing damages and failure modes, setting the basis for subsequent improvements for reliably washable e‐textiles. The research reveals shortcomings and vulnerabilities for each type of track, as well as their current washability level—which differs considerable across the tested circuits. Substrate properties directly influence the washing results. The results do not only provide valuable insight into how and at which points textile integrated circuits need to be optimized to improve washability, but also reveal which pairings of textile properties and circuit types result in more robust and reliabl e‐textiles.

High-performance full-etched fiber-to-chip grating couplers at 3.7-micron wavelength on silicon

Mid-infrared (MIR) silicon photonics have attracted great interest for potential applications in on-chip spectroscopy, free-space communication, and remote imaging. Currently, the high-performance and fabrication-friendly fiber-to-chip grating couplers operating at 3–4 μm wavelength band are still desired urgently. Here, we propose an efficient method for designing a 2D subwavelength grating coupler. The few analytical fitting parameters defining the subwavelength grating periods and fill factors in two dimensions enable a high design degree of freedom and a low search space dimension, resulting in high figure-of-merit and fast convergence simultaneously. The developed 3.7 μm grating coupler showcases record-high coupling efficiency both theoretically (−2.2 dB) and experimentally (−4.4 dB) among the 3–4 μm MIR counterparts. This study provides an effective method for designing fiber-to-chip grating couplers, by which the MIR grating couplers with high performance and fabrication ease are developed, thus paving the way for developing high-performance silicon photonic integrated circuits operating in the MIR wavelength band.

PETAT — an ASIC for simple and efficient readout of large PET scanners

Modern PET scanners based on scintillating crystals use solid state photo detectors for light readout. The small area of these devices is beneficial for spatial resolution, but also leads to a large number of electronic channels to be read out, mostly by application specific integrated circuits (ASICs) containing amplification, noise reduction, hit finding, time stamping and amplitude measurement. Although each ASIC provides up to ≈ 64 channels, a large number of chips is required with the need for auxiliary electronic components like voltage regulators or FPGAs for control and data readout. The FPGAs in turn often require multiple supply voltages and configuration infrastructure, so that PCBs get complicated, cumbersome and power-hungry, in addition to the significant power requirement of the front-end ASICs. We address this issue in the latest generation of our PETA readout ASIC for SiPMs by a simplified control scheme and, in particular, by a hierarchical serial data readout which does not require any additional FPGA. In addition, it provides a time-sorted stream of hit data, allowing early on-detector data reduction and hit pre-processing like the removal of hits with no coincident partner. The simplicity of this readout facilitates a supply scheme where power/ground of multiple ASICs are connected in series instead of the standard parallel connection. This `serial-powering' approach can reduce supply current (while increasing overall supply voltage) so that voltage drop issues in the supply are alleviated.

Magnetostrictive Vibration Suppression via Integration of Current Amplification Negative Capacitor and Current Inversion Semi-Active Control Circuit

When attempting to suppress structural vibrations employing a magnetostrictive transducer, owing to the control force is generated from current, a larger amplification of the current entails superior control performance. The semi-active control theory uses the synchronized switching damping (SSD) technique for structural vibration suppression while requiring a minimal energy supply. However, the absence of external energy input limits the current amplification performance. To address this limitation, this study proposes a novel method that combines semi-active vibration suppression method with negative capacitance to improve the current amplification performance. The proposed circuit switches the circuit status between shunt, inductor-capacitor (LC) electrical oscillation, and negative capacitance circuits. A mathematical model was employed to analyze the current operation, suppression performance, and robustness of the proposed circuit. Further, machine learning and kernel regression model were employed to predict the optimal control force gain. Validation experiments conducted on a 10-bay truss structure identical to the simulation model show that the experimental results align with the simulation predictions. The vibration suppression rates of the proposed method under single-mode and multiple-mode vibrations reached 85.8% and 78.3%, respectively, which are 2.64 and 1.89 times higher than those achieved by conventional methods.

Four-element LC-baluns for power matching arbitrary impedances

Abstract Six four-element balun topologies are introduced that enable complex impedance matching in addition to common-mode rejection. Design equations for these topologies are presented. Three of these networks are universal, while the other three are capable of performing only specific impedance transformations. Examples of these networks were designed and fabricated along with a traditional lattice balun network for an operating frequency of 300 MHz. These networks were verified through extensive electromagnetic simulations and by measuring the fabricated networks. The fabricated novel network examples were able to achieve common-mode rejection ratios above 20 dB, power wave reflection coefficients below −20 dB, and insertion losses of approximately 0.1 dB; these results were similar to or better than the performance of the fabricated traditional lattice balun. The design example networks also provided power matching and low insertion loss over a greater bandwidth compared to the fabricated traditional network. These networks will allow for the footprints of lumped-element balun circuitry to be reduced, which is particularly useful in integrated circuit design. These topologies are also expected to further increase radio-frequency (RF) circuit design flexibility by offering more alternative realizations.

Low-Power Radiation-Hardened Static Random Access Memory with Enhanced Read Stability for Space Applications

In space environments, radiation particles affect the stored values of SRAM cells, and these effects, such as single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), pose a threat to the reliability of systems used in the space industry. To mitigate the impacts of SEUs and SEMNUs, this paper proposes the Read Stability Improved and Low Power (RSLP16T) SRAM cell. It was confirmed that in SEU-induced simulations, all nodes of the RSLP16T could be restored with a charge amount of less than 100 fC. Additionally, it was verified that a similar level of restoration was possible for SEMNUs occurring in pair of storage nodes. The proposed cell achieves a high level of read stability due to a high pull-down cell ratio (current ratio, CR) at the storage nodes and the fact that only a pair of nodes is in contact with the bit lines during read operations. Because all node paths use a stacking structure for internal transistor configuration and a relatively higher number of cells are composed of PMOS, it consumes the least hold power. While these improvements come at the cost of slightly increased delay time and area, performance evaluation revealed that the equivalent quality metric (EQM) was the highest, indicating that the benefits outweigh the drawbacks. The proposed integrated circuit is implemented in the 90 nm CMOS process and operated on 1 V supply voltage.

Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors

The traditional Von Neumann architecture creates bottlenecks due to data movement. The compute-in-memory (CIM) architecture performs computations within memory bit-cell arrays, enhancing computational performance. Edge devices utilizing artificial intelligence (AI) address real-time problems and have established themselves as groundbreaking technology. The 8T structure proposed in this paper has strengths over other existing structures in that it better withstands environmental changes within the SRAM and consumes lower power during memory operation. This structure minimizes reliance on complex ADCs, instead utilizing a simplified voltage differential approach for multiply-and-accumulate (MAC) operations, which enhances both power efficiency and stability. Based on these strengths, it can achieve higher battery efficiency in AI edge devices and improve system performance. The proposed integrated circuit was simulated in a 90 nm CMOS process and operated on a 1 V supply voltage.